Conference Program    Workshop

MONDAY, July 24, 2006, 12:00 PM - 5:00 PM | Room:303
TRACK:SYSTEM LEVEL AND EMBEDDED

  WORKSHOP
  Second Integrated Design System Workshop: How Can We Solve the Challenges of Design System Integration?

  Organizer(s): John Darringer – IBM Corp., Rahul Goyal – Intel Corp., Scott Peterson – LSI Logic Corp., Alva Barney – Hewlett-Packard Co., Bill Bayer – Si2

  The era of "point tools" linked by files is long over. Streamlined integrated design systems are essential to meet today's business demands. Custom chip designers struggle to integrate growing numbers of macros while insuring manufacturability. ASIC and SoC designers must optimize many factors simultaneously to achieve "design closure". Product designers are exploring 3DIC and SiP to fully exploit chip and package synergy and remain competitive.

What does it take to develop effective integrated design systems and when is it coming? Vendors provide solutions for parts of a methodology, but most users want to exploit the best tools from multiple vendors and add proprietary applications to gain a competitive advantage. Progress has been made on standard APIs for sharing data, but much more is needed to enable design systems to keep pace with the industry.

This workshop brings together design system managers and design system providers from the industry's leading companies to assess the state of integrated design systems today, identify the top challenges remaining, and discuss potential solutions in the pipeline and their likely impact will be just over the horizon. What new directions will integrated design systems move into next? What gains in productivity can be expected?

Each session will include a panel to probe deeper into the topics presented and allow your questions to be addressed and your comments be heard.


12:00 Lunch
 
1:00 Part 1: Today’s Challenges and Solutions
Moderator: Scott Peterson - LSI Logic, Bloomington, MN
1:20 What Are the Most Important Challenges for Integrating Design Systems Today?
  Thomas Harms - Infineon Technologies AG, Munich, Germany
 Philippe Magarshack - STMicroelectronics, Crolles Cedex, France
 Rahul Goyal - Intel Corp., Santa Clara, CA
1:50 - What is Coming to Address These Challenges?
  Antun Domic - Synopsys, Inc., San Jose, CA
Ted Vucurevich - Cadence Design Systems, Inc., San Jose, CA
George Janac - Silicon Navigator, Inc., Cupertino, CA
2:20 - PANEL – What Are the Top Priorities and When Will They be Fixed?
  Panel members selected from previous speakers.

3:00 - BREAK
 
Part 2: Tomorrow’s Opportunities
Moderator: Richard Goering – EE Times, Ben Lomond, CA
3:30 - What Are the Next Critical Areas to Address?
  • Evolution of an Integrated Design System
  Yoshi Inoue - Renesas Tech. Corp., Tokyo, Japan
• System-Level Design
  Pat Sheridan - CoWare, Inc., San Jose, CA
• Design for Manufacturability
  Juan-Antonio Carballo - IBM Corp., Austin, TX
• System in Package and 3D ICs
  Bill Price - Philips Semiconductor, San Jose, CA
• IP Modeling
  John Goodenough - ARM, Sunnyvale, CA
4:20 - PANEL: What Major Advances Are Likely to Happen in the Next Four Years?
  Panel members selected from previous speakers.

5:00 Adjourn