1 PANEL: How Will the Fabless Model Survive?
2 Special Session: Why Doesn't My System Work?
3 Hierarchical Synthesis for Mixed-Signal Designs
4 Processor and Communication Centric SoC Design
5 Practical Applications of DFM
6 PANEL: The IC Nanometer Race: What Will It Take to Win?
7 Special Session: Bridging the System to RTL Verification Gap
8 Leakage, Power Analysis and Optimization
9 MPSoC Design Methodologies and Applications
10 Statistical Timing Analysis
11 PANEL: Entering the Hot Zone -- Can You Handle the Heat and Be Cool?
12 Special Session: Reliability Challenges for 65nm and Beyond
13 Power Grid Analysis and Design
14 Advances in Formal Solvers
15 Gate Modeling and Model Order Reduction
16 Special Session: MPSoC Design Tools
17 Special Session: Highlights of ISSCC: Multimedia
18 Buffer Insertion
19 Testing and Validation for Timing Defects
20 Advanced Topics in Processor and System Verification
21 Software for Real-Time Applications
22 PANEL: Building a Standard ESL Design and Verification Methodology: Is It J
23 Invited Session: CAD Challenges for Leading-Edge Multimedia Designs
24 Routing
25 The Test Bin
26 PANEL: Variation-Aware Analysis: Savior of the Nanometer Era?
27 Low Power and Ultra-Low Voltage Design
28 High-Level Exploration and Optimization
29 PANEL: Design Challenges for Next-Generation Multimedia, Game and Entertai
30 CAD for FPGAs
31 Secure Systems
32 Logic Synthesis 1
33 Low-Power, Thermal-Aware Architectures
34 Low Power System Level Design
35 Power-Constrained Design for Multimedia
36 Electrical and Thermal Issues in FPGAs
37 Special Session: Beyond Low-Power Design: Environmental Energy Harvesting
38 Communication-Driven Synthesis
39 Parallelism and Memory Optimizations
40 PANEL: Tomorrow's Analog: Just Dead or Just Different?
41 Nanotubes and Nanowires
42 Simulation Assisted Formal Verification
43 Yield Analysis and Improvement
44 Approaches to Soft Error Mitigation
45 Design/Technology Interaction
46 PANEL: Building a Verification Test Plan: Trading Brute Force for Finesse
47 Special Session: More Moore's Law and More than Moore's Law
48 Formal Specification and Verification Testbench Generation
49 Analysis and Optimization Issues in NoC Design
50 Special Session: Key Technologies for Beyond the Die
51 Analog Design and Design Assistance
52 High-Performance Simulation of Transaction Level and Dataflow Models
53 Nano- and Bio-Chip Design
54 Logic and Sequential Synthesis
55 Low Power Circuit Design
56 Beyond-the-Die Circuit and System Integration
57 New Ideas in Analog/RF Modeling and Simulation
58 Advanced Methods for Interconnect Extraction, Clocks and Reliability
59 PANEL: DFM Where's the Proof of Value?
60 Bounded Model Checking and Equivalence Verification
61 Test Response Compaction and ATPG
62 Placement
100 Decision-Making for Complex SoCs in Consumer Electronic Products
150 Tradeoffs and Choices for Emerging SoCs in High-End Applications

Copyright � 2006 by the Association for Computing Machinery, Inc. (ACM). Permission to make digital or hard copies of portions of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyright for components of this work owned by others that ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permission to republish from: Publications Dept. ACM, Inc. Fax: +1(212) 869-0481 or permissions@acm.org. For other copying of articles that carry a code at the bottom of the first or last page, copying is permitted provided that the per-copy fee indicated in the code is paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923.