|

 
|
 |

Conference Program Technical Session
 |
 |
 |
 |
 |  TUESDAY, July 25, 2006, 4:30 PM - 6:30 PM | Room: 307 |
 |
TOPIC AREA: INTERCONNECT RELIABILITY AND DFM (of special interest to designers)
|
| |
SESSION 12
|
| | Special Session: Reliability Challenges for 65nm and Beyond
 |
| | Chair: David Yeh - Texas Instruments Inc./SRC, Research Triangle Park, NC
| | | Organizers: Joel Phillips, Nagaraj NS
|
| | The intent of this special session is to:
1) Give the EDA community a comprehensive perspective on the problem, explaining what can go wrong (HCI, NBTI, EM, TDDB, SER, ESD, etc.), what will be the major challenges at 65nm and beyond, and how reliability interacts with other design constraints. For example, NBTI not only hurts the reliability of the circuit, but also reduces yield due to the high-temp burn-in process, and higher temperature density due to integration density worsens both EM and NBTI issues.
2) Survey design-in-reliability; what can designers do to build in reliability in products.
3) Present a tools perspective, including the primary effects (HCI, NBTI, EM) for which EDA tools are available, types of tools (dynamic simulation vs. static rule checking), necessary reliability infrastructure and flows that have worked in practice. Finally, new and developing areas of interest, missing pieces, and future opportunities will be discussed.
4) The topics covered in the special session will ensure no rehash of traditional topics and good flow of theory and practice. The session ensures a good balance of key physics phenomena, EDA tools and practical design flows.
|
| | 12.1 |
Reliability Challenges for 45nm and Beyond
|
| | Speaker(s): | Joe McPherson - Texas Instruments Inc., Dallas, TX
|
| | Author(s): | Joe McPherson - Texas Instruments Inc., Dallas, TX
|
| | 12.2 | Design Tools for Reliability Analysis |
| | Speaker(s): | Zhihong Liu - Cadence Design Systems, Inc., San Jose, CA
|
| | Author(s): | Zhihong Liu - Cadence Design Systems, Inc., San Jose, CA
Bruce W. McGaughy - Cadence Design Systems, Inc., San Jose, CA
James Z. Ma - Cadence Design Systems, Inc., San Jose, CA
|
| | 12.3 | Design in Reliability for Communication Designs |
| | Speaker(s): | Uday B. Reddy - Intel Corp., Folsom, CA
|
| | Author(s): | Uday B. Reddy - Intel Corp., Folsom, CA
Murty Dasaka - Intel Corp., Bangalore, India
Pavan Kaipa - Intel Corp., Bangalore, India
|
| | 12.4 | Practical Aspects of Reliability Analysis for IC Designs |
| | Speaker(s): | Thomas Pompl - Infineon Tech. AG, Germany
|
| | Author(s): | Thomas Pompl - Infineon Tech. AG, Germany
Christian Schlunder - Infineon Tech. AG, Germany
Martina Hommel - Infineon Tech. AG, Germany
Heiko Nielen - Infineon Tech. AG, Germany
Jens Schneider - Infineon Tech. AG, Germany
|
|
|
 |