 |
|
|
|
|
WEDNESDAY, July 26, 2006, 8:30 AM - 10:00 AM | Room: 304 |
|
TOPIC AREA: VERIFICATION AND TEST
|
| |
SESSION 19
|
| | Testing and Validation for Timing Defects
|
| | Chair: Cecilia Metra - Univ. of Bologna, Bologna, Italy
|
| | Organizers: Erik Jan Marinissen, Gordon Roberts
|
| | With increasing operation frequencies of ICs, testing and validation of timing defects are becoming more important and challenging.
|
| | 19.1 |
A Flexible and Scalable Methodology for GHz-Speed Structural Test
|
| | Speaker(s): | Vikram Iyengar - IBM Corp., Essex Junction, VT
|
| | Author(s): | Vikram Iyengar - IBM Corp., Essex Junction, VT
Gary Grise - IBM Corp., Essex Junction, VT
Mark Taylor - IBM Corp., Essex Junction, VT
Rudy Farmer - IBM Corp., Essex Junction, VT
|
| | 19.2 | Timing-Based Delay Test for Screening Small Delay Defects |
| | Speaker(s): | Mohammad Tehranipoor - Univ. of Maryland, Baltimore, MD
|
| | Author(s): | Nisar Ahmed - Univ. of Maryland, Baltimore, MD
Mohammad Tehranipoor - Univ. of Maryland, Baltimore, MD
Vinay Jayaram - Texas Instruments Inc., Dallas, TX
|
| | 19.3 | Hold Time Validation on Silicon and the Relevance of Hazards in Timing Analysis |
| | Speaker(s): | Amit Majumdar - Stratosphere Solutions, Inc., Sunnyvale, CA
|
| | Author(s): | Amit Majumdar - Stratosphere Solutions, Inc., Sunnyvale, CA
Wei-Yu Chen - Sun Microsystems, Inc., Sunnyvale, CA
Jun Guo - Sun Microsystems, Inc., Sunnyvale, CA
|
|
Technical Session
