Conference Program    Technical Session

WEDNESDAY, July 26, 2006, 10:30 AM - 12:00 PM | Room: 305
TOPIC AREA:  PHYSICAL DESIGN


   SESSION 24
  Routing
  Chair: Dinesh Gaitonde - Xilinx, Inc., Mountain View, CA
  Organizers: Patrick Groeneveld, Phiroze Parakh

  The first paper in this session introduces a global router with significantly better solution quality. The second paper presents an efficient delay-update technique for network topologies. The third paper presents an innovative method for steiner tree construction via RC network-analysis. Finally, the fourth paper presents a fast timing-driven steiner tree algorithm.

  24.1   BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP
  Speaker(s): Minsik Cho - Univ. of Texas, Austin, TX
  Author(s): Minsik Cho - Univ. of Texas, Austin, TX
David Z. Pan - Univ. of Texas, Austin, TX
  24.2  Steiner Network Construction for Timing Critical Nets
  Speaker(s): Shiyan Hu - Texas A&M Univ., College Station, TX
  Author(s): Shiyan Hu - Texas A&M Univ., College Station, TX
Qiuyang Li - Texas A&M Univ., College Station, TX
Jiang Hu - Texas A&M Univ., College Station, TX
Peng Li - Texas A&M Univ., College Station, TX
  24.3s  Circuit Simulation Based Obstacle-Aware Steiner Routing
  Speaker(s): Yiyu Shi - Univ. of California, Los Angeles, CA
  Author(s): Yiyu Shi - Univ. of California, Los Angeles, CA
Paul Mesa - Univ. of California, Los Angeles, CA
Hao Yu - Univ. of California, Los Angeles, CA
Lei He - Univ. of California, Los Angeles, CA
  24.4s  Timing-Driven Steiner Trees are (Practically) Free
  Speaker(s): C. N. Sze - IBM Corp., Austin, TX
  Author(s): Charles J. Alpert - IBM Corp., Austin, TX
Andrew B. Kahng - Blaze DFM, Inc., Sunnyvale, CA
C. N. Sze - IBM Corp., Austin, TX
Qinke Wang - Univ. of California at San Diego, La Jolla, CA