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Conference Program  Technical Session
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WEDNESDAY, July 26, 2006, 10:30 AM - 12:00 PM | Room: 303 |
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TOPIC AREA: INTERCONNECT RELIABILITY AND DFM
(of special interest to designers)
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SESSION 26
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| | PANEL: Variation-Aware Analysis: Savior of the Nanometer Era?
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| | Chair: William H. Joyner, Jr. - IBM Corp./SRC, Research Triangle Park, NC
| | | Organizers: Shishpal Rawat
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| | VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability. As we go into deep sub micron issues, the analysis is becoming harder due to many secondary effects becoming primary. Panelists will debate the variability trend and present the order of importance of many variability trends (Vdd, Vt, Interconnect, Leff, Gate Width) and their impact on design tools and methodologies.
Variation Panel Extended Abstract
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PANEL: Variation-Aware Analysis: Savior of the Nanometer Era?
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| | Speaker(s): | Vijay Pitchumani - Intel Corp., Santa Clara, CA
Clive D. Bittlestone - Texas Instruments Inc., Dallas, TX
Sani R. Nassif - IBM Corp., Austin, TX
Norma Rodriquez - Advanced Micro Devices, Inc., Sunnyvale, CA
Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI
Riko Radojcic - Qualcomm CDMA Technologies, San Diego, CA
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