Conference Program    Technical Session

WEDNESDAY, July 26, 2006, 10:30 AM - 12:00 PM | Room: 301
TOPIC AREA:  LOW POWER AND THERMAL


   SESSION 27
  Low Power and Ultra-Low Voltage Design
  Chair: Chris Kim - Univ. of Minnesota, Minneapolis, MN
  Organizers: Diana Marculescu, Trevor Mudge

  This session covers topics related to physical leakage models, subthreshold circuit design, and low power voltage assignment.

  27.1   A Fully Physical Model for Leakage Distribution under Process Variations in Nanoscale Double-Gate CMOS
  Speaker(s): Hari Ananthan - Purdue Univ., West Lafayette, IN
  Author(s): Hari Ananthan - Purdue Univ., West Lafayette, IN
Kaushik Roy - Purdue Univ., West Lafayette, IN
  27.2  A PLA Based Asynchronous Micropipelining Approach for Subthreshold Circuit Design
  Speaker(s): Nikhil Jayakumar - Texas A&M Univ., College Station, TX
  Author(s): Nikhil Jayakumar - Texas A&M Univ., College Station, TX
Rajesh Garg - Texas A&M Univ., College Station, TX
Bruce Gamache - Univ. of Colorado, Boulder, CO
Sunil Khatri - Texas A&M Univ., College Station, TX
  27.3s  Subthreshold Logical Effort: A Systematic Framework for Optimal Subthreshold Device Sizing
  Speaker(s): John Keane - Univ. of Minnesota, Minneapolis, MN
  Author(s): John Keane - Univ. of Minnesota, Minneapolis, MN
Tae-Hyoung Kim - Univ. of Minnesota, Minneapolis, MN
Hanyong Eom - Univ. of Minnesota, Minneapolis, MN
Sachin Sapatnekar - Univ. of Minnesota, Minneapolis, MN
Chris Kim - Univ. of Minnesota, Minneapolis, MN
  27.4s  Timing-Constrained and Voltage-Island-Aware Voltage Assignment
  Speaker(s): Huaizhi Wu - Cadence Design Systems, Inc., San Jose, CA
  Author(s): Huaizhi Wu - Cadence Design Systems, Inc., San Jose, CA
Martin D.F. Wong - Univ. of Illinois, Urbana , IL
I-Min Liu - Atoptech, Inc., Santa Clara, CA