Conference Program    Technical Session

WEDNESDAY, July 26, 2006, 2:00 PM - 4:00 PM | Room: 306-308
TOPIC AREA:  SYNTHESIS AND FPGA


   SESSION 28
  High-Level Exploration and Optimization
  Chair: Rishiyur S. Nikhil - Bluespec, Inc., Waltham, MA
  Organizers: Reinaldo Bergamaschi, Rishiyur S. Nikhil

  This session presents five papers which advance the state of the art in high-level synthesis optimization and design space exploration. The first paper presents a new scheduling formulation based on a system of difference constraints. The second paper presents a novel approach for considering clock skew during high-level synthesis. The third and fourth paper present efficient design exploration approaches for high-level design, and the fifth paper presents a method for fast estimation of controller delay from high-level specifications.

  28.1   An Efficient and Versatile Scheduling Algorithm Based On SDC Formulation
  Speaker(s): Zhiru Zhang - Univ. of California, Los Angeles, CA
  Author(s): Jason Cong - Univ. of California, Los Angeles, CA
Zhiru Zhang - Univ. of California, Los Angeles, CA
  28.2  Register Binding for Clock Period Minimization
  Speaker(s): Shih-Hsu Huang - Chung Yuan Christian Univ., Chung Li, Taiwan
  Author(s): Shih-Hsu Huang - Chung Yuan Christian Univ., Chung Li, Taiwan
Chun-Hua Cheng - Chung Yuan Christian Univ., Chung Li, Taiwan
Yow-Tyng Nieh - Chung Yuan Christian Univ., Chung Li, Taiwan
Wei-Chieh Yu - Chung Yuan Christian Univ., Chung Li, Taiwan
  28.3  Towards Automatic Exploration of Arithmetic Circuit Architectures
  Speaker(s): Paolo Ienne - EPFL, Lausanne, Switzerland
  Author(s): Ajay K. Verma - EPFL, Lausanne, Switzerland
Paolo Ienne - EPFL, Lausanne, Switzerland
  28.4s  Design Space Exploration Using Time and Resource Duality with the Ant Colony Optimization
  Speaker(s): Gang Wang - Univ. of California, Santa Barbara, CA
  Author(s): Gang Wang - Univ. of California, Santa Barbara, CA
Wenrui Gong - Univ. of California, Santa Barbara, CA
Brian DeRenzi - Univ. of California, Santa Barbara, CA
Ryan Kastner - Univ. of California, Santa Barbara, CA
  28.5s  Rapid Estimation of Control Delay from High-Level Specifications
  Speaker(s): Preeti R. Panda - Indian Institute of Tech., New Delhi, India
  Author(s): Gagan R. Gupta - Univ. of Wisconsin, Madison, WI
Madhur Gupta - Purdue Univ., West Lafayette, IN
Preeti R. Panda - Indian Institute of Tech., New Delhi, India