Conference Program    Technical Session

TUESDAY, July 25, 2006, 10:30 AM - 12:00 PM | Room: 305
TOPIC AREA:  ANALOG AND CIRCUIT


   SESSION 3
  Hierarchical Synthesis for Mixed-Signal Designs
  Chair: Gerd Vandersteen - IMEC/VUB, Heverlee, Belgium
  Organizers: Geert Van Der Plas, Koen Lampaert

  This session describes the application of hierarchical synthesis and optimization techniques to the design of mixed-signal systems. The first two papers use hierarchical optimization techniques to design a charge pump phase-locked loop and a delta-sigma A/D converter. The third paper describes new methods to generate yield-aware pareto surfaces that link performance tradeoffs and their yield impacts, for use in hierarchical circuit design.

  3.1   A CPPLL Hierarchical Optimization Methodology Considering Jitter, Power and Locking Time
  Speaker(s): Jun Zou - Technische Universitaet Muenchen, Munich, Germany
  Author(s): Jun Zou - Technische Universitaet Muenchen, Munich, Germany
Daniel Mueller - Technische Universitaet Muenchen, Munich, Germany
Helmut Graeb - Technische Universitaet Muenchen, Munich, Germany
Ulf Schlichtmann - Technische Universitaet Muenchen, Munich, Germany
  3.2  Hierarchical Bottom-up Analog Optimization Methodology Validated by a Delta-Sigma A/D Converter Design for the 802.11a/b/g Standard
  Speaker(s): Tom Eeckelaert - Katholieke Univ., Heverlee, Belgium
  Author(s): Tom Eeckelaert - Katholieke Univ., Heverlee, Belgium
Raf Schoofs - Katholieke Univ., Heverlee, Belgium
Georges Gielen - Katholieke Univ., Leuven, Belgium
Michiel Steyaert - Katholieke Univ., Heverlee, Belgium
Willy Sansen - Katholieke Univ., Heverlee, Belgium
  3.3  Generation of Yield-Aware Pareto Surfaces for Hierarchical Circuit Design Space Exploration
  Speaker(s): Saurabh K. Tiwary - Carnegie Mellon Univ., Pittsburgh, PA
  Author(s): Saurabh K. Tiwary - Carnegie Mellon Univ., Pittsburgh, PA
Pragati K. Tiwary - BIT Mesra, Ranchi, India
Rob A. Rutenbar - Carnegie Mellon Univ., Pittsburgh, PA