Conference Program    Technical Session

WEDNESDAY, July 26, 2006, 2:00 PM - 4:00 PM | Room: 305
TOPIC AREA:  SYNTHESIS AND FPGA


   SESSION 30
  CAD for FPGAs
  Chair: William N.N. Hung - Synplicity, Inc., Sunnyvale, CA
  Organizers: Bill Halpin, Steven Teig

  FPGAs have relied on computer-aided design techniques for logic synthesis and physical design since their inception. This session provides novel design tools and methods for solving these "traditional" problem areas, including retiming, clustering, technology mapping and placement.

  30.1   Architecture-Aware FPGA Placement Using Metric Embedding
  Speaker(s): Padmini Gopalakrishnan - Carnegie Mellon Univ., Pittsburgh, PA
  Author(s): Padmini Gopalakrishnan - Carnegie Mellon Univ., Pittsburgh, PA
Xin Li - Carnegie Mellon Univ., Pittsburgh, PA
Lawrence T. Pileggi - Carnegie Mellon Univ., Pittsburgh, PA
  30.2  Efficient SAT-based Boolean Matching for FPGA Technology Mapping
  Speaker(s): Sean A. Safarpour - Univ. of Toronto, Toronto, ON
  Author(s): Sean A. Safarpour - Univ. of Toronto, Toronto, ON
Gregg Baeckler - Altera Corp., San Jose, CA
Richard Yuan - Altera Corp., San Jose, CA
Andreas Veneris - Univ. of Toronto, Toronto, ON
  30.3  Optimal Simultaneous Mapping and Clustering for FPGA Delay Optimization
  Speaker(s): Joey Y. Lin - Magma Design Automation, Inc., Los Angeles, CA
  Author(s): Joey Y. Lin - Magma Design Automation, Inc., Los Angeles, CA
Deming Chen - Univ. of Illinois, Urbana, IL
Jason Cong - Univ. of California, Los Angeles, CA
  30.4  Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction
  Speaker(s): Yu Hu - Univ. of California, Los Angeles, CA
  Author(s): Yu Hu - Univ. of California, Los Angeles, CA
Yan Lin - Univ. of California, Los Angeles, CA
Lei He - Univ of California, Los Angeles, CA
Tim Tuan - Xilinx Corp., San Jose, CA