Conference Program    Technical Session

WEDNESDAY, July 26, 2006, 2:00 PM - 4:00 PM | Room: 304
TOPIC AREA:  SYSTEM LEVEL AND EMBEDDED
(of special interest to designers)

   SESSION 31
  Secure Systems
  Chair: Catherine Gebotys - Univ. of Waterloo, Waterloo, Canada
  Organizers: Pai Chou, Peter Marwedel

  The papers in this session address a critical area in system design: security. VIRTUS enables security through processor virtualization. Network security processor design gives flexibility and scalability for cryptographic functions. A methodology for exploring the security processing software architecture on SoCs is the topic of the third paper. IMPRES presents a HW/SW technique for improving processor security and reliability. Ciphering and integrity checking of data exchanged between a SoC and its external memory is the addressed in the last paper.

  31.1   VIRTUS: A New Processor Virtualization Architecture for Security-Oriented Next-Generation Mobile Terminals
  Speaker(s): Hiroaki Inoue - NEC Corp., Sagamihara, Japan
  Author(s): Hiroaki Inoue - NEC Corp., Sagamihara, Japan
Akihisa Ikeno - NEC Informatec Systems, Ltd., Kawasaki, Japan
Masaki Kondo - NEC Informatec Systems, Ltd., Kawasaki, Japan
Junji Sakai - NEC Corp., Sagamihara, Japan
Masato Edahiro - NEC Corp., Sagamihara, Japan
  31.2  A Network Security Processor Design Based on an Integrated SOC Design and Test Platform
  Speaker(s): Chen-Hsing Wang - National Tsing-Hua Univ., Hsinchu, Taiwan
  Author(s): Chen-Hsing Wang - National Tsing-Hua Univ., Hsinchu, Taiwan
Chih-Yen Lo - National Tsing-Hua Univ., Hsinchu, Taiwan
Min-Sheng lee - National Tsing-Hua Univ., Hsinchu, Taiwan
Jen-Chieh Yeh - National Tsing-Hua Univ., Hsinchu, Taiwan
Chih-Tsun Huang - National Tsing-Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu - National Tsing-Hua Univ., Hsinchu, Taiwan
  31.3  Software Architecture Exploration for High-Performance Security Processing on a Multiprocessor Mobile SoC
  Speaker(s): Divya Arora - Princeton Univ., Princeton, NJ
  Author(s): Divya Arora - Princeton Univ., Princeton, NJ
Srivaths Ravi - NEC-Labs America, Princeton, NJ
Anand Raghunathan - NEC-Labs America, Princeton, NJ
Murugan Sankaradass - NEC-Labs America, Princeton, NJ
Niraj Jha - Princeton Univ., Princeton, NJ
Srimat T. Chakradhar - NEC-Labs America, Princeton, NJ
  31.4s  IMPRES: Integrated Monitoring for Processor REliability and Security
  Speaker(s): Sridevan Parameswaran - Univ. of New South Wales, Sydney, Australia
  Author(s): Roshan G. Ragel - Univ. of New South Wales, Sydney, Australia
Sridevan Parameswaran - Univ. of New South Wales, Kensington, Australia
  31.5s  A Parallelized Way to Provide Data Encryption and Integrity Checking on a Processor-Memory Bus
  Speaker(s): Reouven Elbaz - STMicroelectronics, Montpellier, France
  Author(s): Reouven Elbaz - STMicroelectroncis, Montpellier, France
Lionel Torres - LIRMM, Montpellier, France
Gilles Sassatelli - LIRMM, Montpellier, France
Pierre Guillemin - STMicroelectronics, Rousset, France
Michel Bardouillet - STMicroelectronics, Rousset, France
Albert Martinez - STMicroelectronics, Rousset, France