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TUESDAY, July 25, 2006, 10:30 AM - 12:00 PM | Room: 304 |
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TOPIC AREA: SYSTEM LEVEL AND EMBEDDED
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SESSION 4
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| | Processor and Communication Centric SoC Design
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| | Chair: Johannes Stahl - CoWare, Inc., San Jose, United States
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| | Organizers: Brian Bailey, Rainer Leupers
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| | Multi-processor systems-on-chip (MPSoCs) are becoming a necessary way to balance performance, power and reliability while maintaining the maximum degree of flexibility.
The first paper proposes the use of bus scenarios for an optimized time budget assignment to system tasks. The second paper proposes a new approach to implement custom processor instruction set extensions. The third paper focuses on optimization of scratch-pad memory hierarchies for MPSoC architectures, while the last paper deals with handling both transient and permanent faults in a tiled architecture, targeting single program, multiple data applications.
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| | 4.1 |
A Real Time Budgeting Method for Module-Level-Pipelined Bus Based System using Bus Scenarios
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| | Speaker(s): | Tadaaki Tanimoto - Renesas Technology Corp., Kodaira Tokyo, Japan
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| | Author(s): | Tadaaki Tanimoto - Renesas Technology Corp., Kodaira Tokyo, Japan
Seiji Yamaguchi - Osaka Univ., Suita Osaka, Japan
Akio Nakata - Osaka Univ., Suita Osaka, Japan
Teruo Higashino - Osaka Univ., Suita Osaka, Japan
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| | 4.2 | Exploiting Forwarding to Improve Data Bandwidth of Instruction-Set Extensions |
| | Speaker(s): | Ramkumar Jayaseelan - National Univ. of Singapore, Singapore,
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| | Author(s): | Ramkumar Jayaseelan - National Univ. of Singapore, Singapore,
Haibin Liu - National Univ. of Singapore, Singapore,
Tulika Mitra - National Univ. of Singapore, Singapore,
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| | 4.3s | Multiprocessor System-on-Chip Data Reuse Analysis for Exploring Customized Memory Hierarchies |
| | Speaker(s): | Ilya Issenin - Univ. of California, Irvine, CA
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| | Author(s): | Ilya Issenin - Univ. of California, Irvine, CA
Erik Brockmeyer - IMEC, Leuven, Belgium
Bart Durinck - IMEC, Leuven, Belgium
Nikil Dutt - Univ. of California, Irvine, CA
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| | 4.4s | Modeling a Fault-Tolerant Multiprocessor SoC with Run-time Fault Recovery |
| | Speaker(s): | Xinping Zhu - Northeastern Univ., Boston, MA
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| | Author(s): | Xinping Zhu - Northeastern Univ., Boston, MA
Wei Qin - Boston Univ., Boston, MA
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Technical Session
