Conference Program    Technical Session

THURSDAY, July 27, 2006, 8:30 AM - 10:00 AM | Room: 305
TOPIC AREA:  VERIFICATION AND TEST


   SESSION 42
  Simulation Assisted Formal Verification
  Chair: Andrew Piziali - Cadence Design Systems, Inc., Parker, TX
  Organizers: Harry Foster, Richard Ho

  The papers in this session utilize simulation to improve the results of formal verification, both for model checking and for equivalence checking. One paper explores the verification of a serial protocol and bridge, one paper describes a technique for finding very long counter-examples (bugs) and our final paper utilizes simulation and data mining techniques to discover global constraints that can be used in a number of applications.

  42.1   Directed-Simulation Assisted Formal Verification of Serial Protocol and Bridge
  Speaker(s): Raj S. Mitra - Texas Instruments Inc., Bangalore, India
  Author(s): Saurav Gorai - Mentor Graphics Corp., Noida, India
Saptarshi Biswas - Texas Instruments Inc., Bangalore, India
Lovleen Bhatia - Texas Instruments Inc., Bangalore, India
Praveen Tiwari - Texas Instruments Inc., Bangalore, India
Raj S. Mitra - Texas Instruments Inc., Bangalore, India
  42.2  Guiding Simulation with Increasingly Refined Abstract Traces
  Speaker(s): Kuntal V. Nanshi - Univ. of Colorado, Boulder, CO
  Author(s): Kuntal V. Nanshi - Univ. of Colorado, Boulder, CO
Fabio Somenzi - Univ. of Colorado, Boulder, CO
  42.3  Mining Global Constraints for Improving Bounded Sequential Equivalence Checking
  Speaker(s): Weixin Wu - Virginia Tech., Blacksburg, VA
  Author(s): Weixin Wu - Virginia Tech., Blacksburg, VA
Michael Hsiao - Virginia Tech., Blacksburg, VA