Conference Program    Technical Session

THURSDAY, July 27, 2006, 8:30 AM - 10:00 AM | Room: 304
TOPIC AREA:  PHYSICAL DESIGN


   SESSION 43
  Yield Analysis and Improvement
  Chair: Evanthia Papadopoulou - IBM Corp., Yorktown Heights, NY
  Organizers: Fook-Luen Heng, Patrick Groeneveld

  Yield analysis and improvement have gained more attention due to new defect mechanisms in the nano-technology era. The first paper is an early attempt to derive a mathematical model to predict yield based on process information. The second paper addresses double via insertion during the routing phase. The third paper solves the antenna avoidance problem by considering the actual antenna ratio constraint.

  43.1   An IC Manufacturing Yield Model Considering Intra-Die Variations
  Speaker(s): Jianfeng Luo - Synopsys, Inc., Mountain View, CA
  Author(s): Jianfeng Luo - Synopsys, Inc., Mountain View, CA
Subarna Sinha - Synopsys, Inc., Mountain View, CA
Qing Su - Synopsys, Inc., Mountain View, CA
Jamil Kawa - Synopsys, Inc., Mountain view, CA
Charles Chiang - Synopsys, Inc., Mountain View, CA
  43.2  Novel Full-Chip Gridless Routing Considering Double-Via Insertion
  Speaker(s): Huang-Yu Chen - National Taiwan Univ., Taipei, Taiwan
  Author(s): Huang-Yu Chen - National Taiwan Univ., Taipei, Taiwan
Mei-Fang Chiang - National Taiwan Univ., Taipei, Taiwan
Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan
Lumdo Chen - UMC, Hsinchu Science Park, Taiwan
Brian Han - UMC, Hsinchu Science Park, Taiwan
  43.3  Optimal Jumper Insertion for Antenna Avoidance under Ratio Upper-Bound
  Speaker(s): Jia Wang - Northwestern Univ., Evanston, IL
  Author(s): Jia Wang - Northwestern Univ., Evanston, IL
Hai Zhou - Northwestern Univ., Evanston, IL