Conference Program    Technical Session

THURSDAY, July 27, 2006, 8:30 AM - 10:00 AM | Room: 303
TOPIC AREA:  INTERCONNECT RELIABILITY AND DFM
(of special interest to designers)

   SESSION 44
  Approaches to Soft Error Mitigation
  Chair: Subashish Mitra - Stanford Univ., Stanford, CA
  Organizers: Dennis Sylvester, Haihua Su

  This session describes new approaches to reducing soft error rates in modern ICs, particularly in combinational logic, but also in memory structures. The first paper details a symbolic framework to analyze error susceptibility that then drives selective gate sizing to harden the circuit with limited overheads. The second paper incorporates shadow gates on highly critical gates to achieve radiation hardening with acceptable area and delay penalties. The final paper proposes new content-addressable memory structures to achieve soft error rate improvements.

  44.1   MARS-C: Modeling and Reduction of Soft Errors in Combinational Circuits
  Speaker(s): Natasa Miskov-Zivanov - Carnegie Mellon Univ., Pittsburgh, PA
  Author(s): Natasa Miskov-Zivanov - Carnegie Mellon Univ., Pittsburgh, PA
Diana Marculescu - Carnegie Mellon Univ., Pittsburgh, PA
  44.2  A Design Approach for Radiation-­Hard Digital Electronics
  Speaker(s): Rajesh Garg - Texas A&M Univ., College Station, TX
  Author(s): Rajesh Garg - Texas A&M Univ., College Station, TX
Nikhil Jayakumar - Texas A&M Univ., College Station, TX
Sunil P. Khatri - Texas A&M Univ., College Station, TX
Gwan Choi - Texas A&M Univ., College Station, TX
  44.3  A Family of Cells to Reduce the Soft-Error-Rate in Ternary-CAM
  Speaker(s): Navid Azizi - Univ. of Toronto, Toronto, ON
  Author(s): Navid Azizi - Univ. of Toronto, Toronto, ON
Farid N. Najm - Univ. of Toronto, Toronto, ON