Conference Program    Technical Session

THURSDAY, July 27, 2006, 8:30 AM - 10:00 AM | Room: 301
TOPIC AREA:  INTERCONNECT RELIABILITY AND DFM
(of special interest to designers)

   SESSION 45
  Design/Technology Interaction
  Chair: Jerry D. Hayes - IBM Corp., Essex Junction, VT
  Organizers: Sani R. Nassif

  Technology scaling has drastically exacerbated the complexity and amount of data required to achieve productive design/technology interaction. This session shows examples of the excellent work going on in the DFM community on ensuring the best possible coupling between the design and fabrication phases.

  45.1   Process Variation Aware OPC with Variational Lithography Modeling
  Speaker(s): Peng Yu - Univ. of Texas, Austin, TX
  Author(s): Peng Yu - Univ. of Texas, Austin, TX
Sean X. Shi - Univ. of Texas, Austin, TX
David Z. Pan - Univ. of Texas, Austin, TX
  45.2  Modeling of Intra-die Process Variations for Accurate Analysis and Optimization of Nano-scale Circuits
  Speaker(s): Sarvesh Bhardwaj - Arizona State Univ., Tempe, AZ
  Author(s): Sarvesh Bhardwaj - Arizona State Univ., Tempe, AZ
Sarma Vrudhula - Arizona State Univ., Tempe, AZ
Praveen Ghanta - Arizona State Univ., Tempe, AZ
Yu Cao - Arizona State Univ., Tempe, AZ
  45.3s  Computation of Accurate Interconnect Process Parameter Values for Performance Corners under Process Variations
  Speaker(s): Frank Huebbers - Northwestern Univ., Evanston, IL
  Author(s): Frank Huebbers - Northwestern Univ., Evanston, IL
Ali Dasdan - Yahoo, Sunnyvale, CA
Yehea Ismail - Northwestern Univ., Evanston, IL
  45.4s  Standard Cell Characterization Considering Lithography Induced Variations
  Speaker(s): Ke Cao - Qualcomm Inc., San Diego, CA
  Author(s): Ke Cao - Qualcomm Inc., San Diego, CA
Sorin Dobre - Qualcomm Inc., San Diego, CA
Jiang Hu - Texas A&M Univ., College Station, TX