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Conference Program  Technical Session
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THURSDAY, July 27, 2006, 10:30 AM - 12:00 PM | Room: 306-308 |
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TOPIC AREA: VERIFICATION AND TEST
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SESSION 46
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| | PANEL: Building a Verification Test Plan: Trading Brute Force for Finesse
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| | Chair: Sharad Malik - Princeton Univ., Princeton, NJ
| | | Organizers: Francine Bacchini
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| | The pain of functional verification is intensifying. Building the right verification test plan can reduce this pain - trading brute force for finesse - while enabling greater predictability, more aggressive innovation and late stage spec changes made with confidence. Users and suppliers debate the optimal mix of formal, simulation, hardware acceleration and emulation, examining ways to ensure new features aren't dropped pre-tapeout from 'inadequate verification'.
Verification Panel Extended Abstract
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| | 46.1 |
PANEL: Building a Verification Test Plan: Trading Brute Force for Finesse
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| | Speaker(s): | Doron Stein - Cisco Systems, Inc., Netanya, Israel
Raj S. Mitra - Texas Instruments Inc., Bangalore, India
Janick Bergeron - Synopsys, Inc., Ottawa, Ontario
Harry D. Foster - Mentor Graphics Corp., Addison, TX
Andrew Piziali - Cadence Design Systems, Inc., Parker, TX
Catherine Ahlschlager - Sun Microsystems, Inc., Sunnyvale, CA
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