Conference Program    Technical Session

THURSDAY, July 27, 2006, 10:30 AM - 11:30 AM | Room: 305
TOPIC AREA:  VERIFICATION AND TEST


   SESSION 48
  Formal Specification and Verification Testbench Generation
  Chair: Michael Theobald - D.E. Shaw Research, New York, NY
  Organizers: Alan Hu, Erich Marschner

  Formal verification today typically involves verification of a design with respect to its specification. This session presents formal methods applied to earlier stages of the verification process, including formal methods for investigating the quality of a specification, and for generating testbenches from a specification.

  48.1   Formal Analysis of Hardware Requirements
  Speaker(s): Marco Roveri - ITC Irst, Povo, Italy
  Author(s): Ingo Pill - Graz Univ. of Tech., Graz, Austria
Simone Semprini - ITC Irst, Povo, Italy
Roberto Cavada - ITC Irst, Povo, Italy
Marco Roveri - ITC Irst, Povo, Italy
Roderick Bloem - Graz Univ. of Tech., Graz, Austria
Alessandro Cimatti - ITC Irst, Povo, Italy
  48.2  Cancelled
  48.3  Test Generation Games from Formal Specifications
  Speaker(s): Ansuman Banerjee - Indian Institute of Tech., Kharagpur, India
  Author(s): Ansuman Banerjee - Indian Institute of Tech., Kharagpur, India
Bhaskar Pal - Indian Institute of Tech., Kharagpur, India
Sayantan Das - Indian Institute of Tech., Kharagpur, India
Abhijeet Kumar - Indian Institute of Tech., Kharagpur, India
Pallab Dasgupta - Indian Institute of Tech., Kharagpur, India