Conference Program    Technical Session

TUESDAY, July 25, 2006, 2:00 PM - 4:00 PM | Room: 307
TOPIC AREA:  VERIFICATION AND TEST
(of special interest to designers)

   SESSION 7
  Special Session: Bridging the System to RTL Verification Gap
  Chair: Brian Bailey - Verification Consultant, Oregon City, OR
  Organizers: Anmol Mathur

  System-level models in C/C++ or SystemC are gaining widespread acceptance for developing golden functional reference models, as vehicles for micro-architecture exploration and as platforms for software development. Transaction-level models are used to provide a communication-accurate view of a design that simulates 100 to 1000 times faster than RTL. Since the high-level models can be simulated with real applications, the design team can often get a high level of confidence in the functional correctness of this model. Design teams are often spending 30-50% of their overall design cycle in this phase to generate the functional reference model and decide on the micro-architecture.

  7.1   Use of C/C++ Models for Architecture Exploration and Verification of DSPs
  Speaker(s): David Brier - Texas Instruments Inc., Dallas, TX
  Author(s): David Brier - Texas Instruments Inc., Dallas, TX
Raj S. Mitra - Texas Instruments Inc., Bangalore, India
  7.2  Maintaining Consistency Between SystemC and RTL System Designs
  Speaker(s): Christopher Lennard - ARM Ltd., Cambridge, United Kingdom
  Author(s): Christopher Lennard - ARM Ltd., Cambridge, United Kingdom
Alistair Bruce - ARM Ltd., Sheffield, United Kingdom
Andrew Nightingale - ARM Ltd., Cambridge, United Kingdom
Nizar Romdhane - ARM Ltd., Cambridge, United Kingdom
M M Kamal Hashmi - Spiratech Ltd., Manchester, United Kingdom
Steve Beavis - Spiratech Ltd., Manchester, United Kingdom
  7.3  SystemC Transaction Level Models and RTL Verification
  Speaker(s): Stuart Swan - Cadence Design Systems, Inc., Redwood City, CA
  Author(s): Stuart Swan - Cadence Design Systems, Inc., Redwood City, CA
  7.4  Towards a C++-Based Design Methodology Facilitating Sequential Equivalence Checking
  Speaker(s): Venkat Krishnaswamy - Calypto Design Systems, Inc., Santa Clara, CA
  Author(s): Venkat Krishnaswamy - Calypto Design Systems, Inc., Santa Clara, CA
Phillipe Georgelin - ST Microelectronics, Crolles, France