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| THURSDAY, June 7, 2007, 9:00 AM - 11:00 AM | Room: 6A |
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TOPIC AREA: VERIFICATION AND TEST
(of special interest to designers)
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SESSION 41
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| | PANEL: Verification Coverage: When is Enough Enough?
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| | Chair: Alan Hu - Univ. of British Columbia, Vancouver, BC, Canada
| | | Organizers: Francine Bacchini - Francine Bacchini, Inc. |
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For EDA users, verification is a challenging and time-consuming process. Recent tools have driven powerful new methodologies, and have renewed debate on the issue of coverage interoperability among heterogeneous verification tools and their respective handling of coverage data. New methodologies hold promise for better decision-making, as does a baseline standard for coverage interoperability. Learn from industry-leading EDA users and vendors as they explore these emerging solutions to the ever-growing challenge of functional verification.
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| | 41.1 |
Verification Coverage: When is Enough Enough?
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| | Speaker(s): | Tom Fitzpatrick - Mentor Graphics Corp., San Jose, CA
David J. Lacey - Hewlett-Packard Co., Richardson, TX
Andrew Piziali - Consultant for Cadence Design Systems, Inc., Parker, TX
Rajeev Ranjan - Jasper Design Automation, Inc., Mountain View, CA
Mercedes Tan - Sun Microsystems, Inc., Sunnyvale, CA
Avi Ziv - IBM Corp., Haifa, Israel
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Technical Session