Follow Us

Exhibitor Resource Center

Rocketick - GPU based simulation acceleration

RocketSim™ solves functional verification bottlenecks by complementing simulators with a GPU-based acceleration solution that offers 10x faster simulations for highly complex designs.

The Verification Gap
Functional verification is a severe bottleneck in chip design projects. The ever-growing chip density and complexity impacts the time it takes simulators to complete each run. In some applications simulations can take days to complete, affecting the product’s time-to-market or forcing tape-out before full testing is completed.

Complementing Simulators with GPU-based Acceleration
RocketSim solves the simulator’s bottleneck challenge by offloading most time-consuming calculations to an ultra-fast GPU-based engine. Unlike hardware based accelerators, RocketSim works from within the familiar simulator environment and runs alongside the existing test bench, eliminating ramp-up time while providing bit-precise results.  

Enabling Full Debug Visibility for Large Designs 
RocketSim supports large and complex designs (over 600M gates), while offering full visibility of your design. Thanks to its very efficient memory utilization, you can finally expand your current verification scope to include larger designs and to verify more complex tests.

Runs from within the Simulator Environment
RocketSim is transparent to the user, who continues to use the existing simulator. Working from within the familiar host simulator environment, RocketSim supports any user PLI modules, runs PLI put/get/force values from signals and RAMs as part of its acceleration, and can run alongside the existing test bench. 

Main Features

  • Accelerates functional Verilog simulation by over 10X
  • Cuts memory usage by over 80%
  • Compatible with the leading simulators
  • Fast compilation of large designs
  • Full debug visibility (VCD, FSDB)
  • Completely scalable- 1B gate capacity
  • Compliant with Verilog IEEE 1364-2001, 1364-2005, VHDL, and System Verilog
  • PLI-compliant interface
  • Runs alongside the test bench
  • Highly scalable
  • No ramp-up 

CAE Gate Level
  • Acceleration and Emulation - Gate Level
  • Gate Level Simulation
CAE RT Level
  • Acceleration and Emulation - RT Level
  • Mixed-Language Simulation
  • Verification
  • Verilog Simulation
  • VHDL Simulation
Embedded Systems
  • ESL Co-Verification
  • ESL Simulation

Design Automation Conference Sponsors IEEE Solid State Circuits Society Electronic Design Automation Consortium CEDA - IEEE Council on Electronic Design Automation SIGDA Special Interest Group - Design Automation