DeFacTo EDA tools help achieving “Design & DFT” closure at RTL. Several needs are covered by the SIGNOFF and the STAR products: IP Integration, Design Verification & DFT Signoff needs. SIGNOFF is a complete solution for RTL Testability Evaluation, Debug & Enhancement. It is daily used by DFT engineers and RTL designers. STAR is fully customizable RTL editing and verification which cover several design insertion and design verifications areas. It is used as add-on toolbox to current design & verification EDA tools: * STAR-CK : Structural clock tree verification at RTL * STAR-Power : RTL structural power verification and automatic insertion of low power structures * STAR-Build : Automatic block merge and RTL generation * STAR-ECO : Gate-level and RTL Engineering Change Order with automated generation of gate and RTL * STAR-Debug : RTL and gate-level design exploration, pin to pin tracing and debug of complex IP cores and SoCs.
CAE RT Level- DFT Tools
- Power Design
- RTL Design and Entry
- Verification