MONDAY June 03, 1:30pm - 5:30pm | N255
Tutorial 6: Analog IP Migration and Verification

Michael Pronath - MunEDA GmbH, Unterhaching, Germany
Benjamin Prautsch - Fraunhofer IIS, Institutsteil EAS, Dresden, Germany
Hidekazu Kojima - Rohm, Japan
Russell Mohn - inPlay Technologies, CA
Pierluigi Daglio - STMicroelectronics, Agrate, Italy
Michael Pronath - MunEDA GmbH, Unterhaching, Germany
Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. Efficient IP re-use is a key capability of a design flow that meets time-to-market requirements and is cost-effective. When porting full custom IP to a new target process technology for the purpose of IP reuse, designers must consider many influence factors and effects, operating conditions, random variations in the manufacturing process, device aging, as well as layout-dependent effects. Sizing circuits to meet specs at all process corners and operating conditions while simultaneously minimizing power consumption and/or area is a major challenge in full custom design. Automated sizing of analog/RF and digital full custom circuits has matured greatly in recent years, evolving from early attempts at analog synthesis to modern process technology-oriented optimization tools for design centering. In this tutorial we will discuss automated sizing methodologies that improve design quality and design time significantly in productive full custom migration flows today. Layout design efforts also tend to be a critical issue when targeting time-to-market constraints. In this tutorial, new approaches for IP development---intelligent IP (IIP)---will be presented and discussed for easy reuse of building blocks of the source IP in the target technology. Intelligent IP, technology independent methodologies and algorithms for fast layout migration, analysis and sizing are required to migrate full-custom IP to a new process technology efficiently. We will discuss constraint-based layout-aware optimization tools using predefined layout templates or pure automation as well as analog generators containing expert knowledge. While optimization is a holistic top-down approach, generators allow parameterized and fast bottom-up generation of critical schematic and layout parts, pre-planned by experienced designers. In this tutorial we’ll discuss challenges, EDA solutions and industrial design cases for migrating, analyzing and retargeting IP between process technologies, particularly focusing on analog and full-custom IP migration and back end design. Experts from semiconductor industry, semiconductor research institutes and EDA tool providers will present outstanding solutions and their applications.