SUNDAY June 01, 1:00pm - 5:00pm | Room 309
Paolo Giusto - General Motors Company, Palo Alto, CA
Ahmed Jerraya - Univ. Grenoble Alpes - CEA, LETI, Grenoble, France
Menno Lindwer - Intel Corp., Eindhoven, The Netherlands
Louis-Noel Pouchet - Univ. of California, Los Angeles, CA
Yosinori Watanabe - Cadence Design Systems, Inc., San Jose, CA
Michael Zimmer - Univ. of California, Berkeley, CA
Albert Cohen - École Normale Supérieure, Paris, France
In the last few years, multiprocessors have penetrated the embedded market. Several platform providers (e.g. Qualcomm, NVidia, TI, STM, to name but a few) now propose multicore architectures with scalable performance. These architectures are able to cope with the rising processing needs, while keeping power consumption under control. They provide developers with a lot of flexibility and offer efficient power monitoring and control features. However these evolutions help sustain the electronic system market growth at the expense of software development cost. This is because concurrent programming is inherently more difficult than sequential programming, and it is less widely taught in universities.
It is widely reported that the cost of developing the support software libraries that need to be shipped with a new hardware platform is approaching and may soon exceed the hardware design costs. A significant portion of this cost is due to the above-mentioned difficulty of concurrent multicore programming. Hardware architectures evolve faster than software tools, and the specification and mapping of applications onto new multicore architectures, especially heterogeneous ones, becomes more complex. Managing voltage and frequency in the presence of rapidly varying computational loads and real-time deadlines can be overwhelming. It can lead to under-exploiting the power saving opportunities, and even to resounding battery life problems.
In summary, the lack of efficient concurrent software development tools and of platform abstraction middleware hinders adoption of new architectures and increases software development costs. The electronic industry therefore has to face a new challenge by introducing efficient tools capable to assist designers in these tasks. The main objective of this workshop is to bring together key players from both industry and academia, to discuss the challenges and outline possible solutions, while verifying their applicability to real systems.
This workshop is organized by the FP7 PHARAON project consortium. The project, which is co-funded by the European Commission, is aimed at reducing mapping complexity, increasing performance and reducing power consumption for multi-core platforms.
It will cover the following topics:
- Multi-Processor platforms as innovation drivers for security and safety applications: What are the technical requirements to be solved
- Deploying Multiprocessor Technologies in Mainstream Development Cycles: Design Challenges and Opportunities for Automotive OEMs
- Modeling and Mapping Medical Imaging Applications to Heterogeneous Hardware
- Building, programming, and validating low-power heterogeneous multi-core image processors
- Advanced semiconductor technologies enabling high performance energy efficient MPSoCs
- Software driven power management analysis with virtual platforms
- Energy efficiency of flexible precision-timed processors.