IC designs are continually growing larger and more complex; higher instance/net counts, higher clock frequency, lower power targets and tighter timing constraints. Meanwhile time-to-market pressures are stronger than ever. EDA tools and complementary methodologies are key to addressing the challenges faced in this environment. This tutorial will present design techniques and tricks for driving design closure to achieve power, performance, and area constraints. Design tasks such as placement congestion reduction, guiding clock tree synthesis, post-clock optimization, signal routing, wired optimization, and post-routing sign-off will be discussed. Each topic will include a discussion of relevant EDA tools, physical design methodologies using those tools and ASIC design examples. The target audience for this tutorial is physical designers and physical design focused EDA tool/methodology developers.
DAC is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP).
DAC 2017 will be held in Austin, Texas, at the Austin Convention Center. Get details about travel, hotels, and area attractions in one convenient spot.