MONDAY June 02, 10:30am - 12:00pm | Room 305
Paul Marchal - IMEC, San Francisco, CA
As the semiconductor industry migrates toward extreme monolithic foundry level 3D heterogeneous structures for mixed-signal components and systems, 2.5D/3D silicon interposer and through silicon via (TSV) technology will play a significant role in next generation 3D packaging technologies. 2.5D/3D approaches, such as interposers, enable heterogeneous device integration at virtually any process node. 2.5D/3D integration technologies rely on numerous leading edge technologies such as, TSV technology, wafer thinning/handling technology and micro-bump technology.
Architecting a cost effective and robust interposer that satisfies electrical, thermal-stress, manufacturing and yield requirement is key to successful 2.5D/3D integration. We will demonstrate methodology for performing Path-finding, design optimization and system exploration of 2.5D/3D devices in the context of multiple systems and its direct impact on performance, cost and time to market.
To help designers in adopting 2.5/3D technology, we will also review the most important (design) challenges: assembly yield and impact of die size and substrate material hereon; power density and thermal performance; electrical performance of the interconnects; design for test.
Finally, we will discuss our latest technology developments, such as the active lite interposer with embedded passives and ESD components and how they could be used to create more cost-effective 3D stacks.