MONDAY June 02, 10:30am - 12:00pm | Room 305
Tutorial 5: Advances in 2.5D/3D Silicon Interposer Packaging Technologies

Farhang Yazdani - BroadPak Corp., San Jose, CA
Paul Marchal - IMEC, San Francisco, CA
Farhang Yazdani - BroadPak Corp., San Jose, CA

As the semiconductor industry migrates toward extreme monolithic foundry level 3D heterogeneous structures for mixed-signal components and systems, 2.5D/3D silicon interposer and through silicon via (TSV) technology will play a significant role in next generation 3D packaging technologies. 2.5D/3D approaches, such as interposers, enable heterogeneous device integration at virtually any process node. 2.5D/3D integration technologies rely on numerous leading edge technologies such as, TSV technology, wafer thinning/handling technology and micro-bump technology.

Architecting a cost effective and robust interposer that satisfies electrical, thermal-stress, manufacturing and yield requirement is key to successful 2.5D/3D integration.  We will demonstrate methodology for performing Path-finding, design optimization and system exploration of 2.5D/3D devices in the context of multiple systems and its direct impact on performance, cost and time to market.

To help designers in adopting 2.5/3D technology, we will also review the most important (design) challenges:  assembly yield and impact of die size and substrate material hereon; power density and thermal performance; electrical performance of the interconnects; design for test.

Finally, we will discuss our latest technology developments, such as the active lite interposer with embedded passives and ESD components and how they could be used to create more cost-effective 3D stacks.

Farhang Yazdani is the President and CEO of BroadPak Corporation; A company that offers total solution to develop and launch low cost 2.5D/3D products. With over 17 years of experience in semiconductor packaging industry, he is widely regarded as an expert on 2.5D/3D packaging technologies. He is a frequent speaker at international events. Previously, he served in various management, technical and advisory positions with leading semiconductor companies worldwide. He has numerous publications and US patents issued and pending in the area of Packaging and Assembly, serves on various technical committees and is a frequent reviewer for IEEE Journal of Advanced Packaging. He has undergraduate and graduate degrees in Chemical Engineering and Mechanical Engineering from the University of Washington, Seattle. He is a member of AICHE, ASME, IEEE, IMAPS, SPE and the Society of Rheology.

Paul Marchal holds a position as director of technical marketing at imec. He is responsible for defining technology roadmaps for imec’s advanced packaging solutions in close collaborations with US customers. Before he initiated and led imec’s 3D design initiative and insite program. Together with his team, he built first DRAM-on-logic prototype. He holds an engineering degree and Ph.D. in electrical engineering from the Katholieke Universiteit Leuven, Belgium. Paul’s research interests are energy-efficient system integration through the use of advanced packaging and semiconductor technologies. He has published more than 40 papers in peer-reviewed international journals and conferences and holds more than 8 patents. He is a frequently invited speaker at conferences on the topic of 3D systems. He received best European paper award at ISSCC, best paper nomination at DAC, best paper award at ICMTS conference. He was member of the several program and executive committees (ASSCC, 3D IC, DATE). He was awarded the ITW fellowship for his Ph.D. from the Flemish government and received the imec’s outstanding Ph.D. award.