FinFETs and tri-gate FETs have extended Moore's law down to a gate length of 20-15nm. A Silicon Nanowire Transistor (NWT) is one of the most promising devices which could give further gate length scaling to 10-5 nm, potentially to 3 nm. At these dimensions, quantum confinement and effects should be understood for proper development of functional CMOS circuits and robust design methodology.
The tutorial will cover briefly the transition needed from a conventional planar transistor to a FinFET in device physics, circuit and methodology, followed by a detailed description of enhancing channel control by a gate through higher-dimensional multi-gate structures, Gate-All-Around Nanowire FETs. It can have vertical or horizontal transistor architectures, each with its own advantages and possible drawbacks. Discussion of circuit prospects of NWT in the fields of CMOS logic, volatile and non-volatile memory, and integrated sensors will be concluded by expected changes in circuits and methodology for transition from FinFET to NWT, including quantum effects.
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DAC 2017 will be held in Austin, Texas, at the Austin Convention Center. Get details about travel, hotels, and area attractions in one convenient spot.