MONDAY June 02, 10:30am - 12:00pm | Room 304
TOPIC AREA: EDA
KEYWORD: EMBEDDED SYSTEM METHODOLOGIES
EVENT TYPE: MONDAY TUTORIAL
Tutorial 11: Optimizing ARM-Based SoCs for Performance and Speeding System Validation

Speakers:
Poonacha Kongetira - NetSpeed Systems, San Jose, CA
Nick Heaton - Cadence Design Systems, Inc., San Jose, CA
Robert Kaye - Arm, Ltd., Cambridge, United Kingdom
Organizer:
Frank Schirrmeister - Cadence Design Systems, Inc., San Jose, CA
Design of multi-core systems requires a sophisticated approach to architecture of the SoC, and a thorough methodology for embedded software development. Ensuring that expected performance targets are achieved is becoming more and more difficult due to the number of processors and the expanding configuration choices of system interconnect. Developing hardware and software in parallel is often facing significant barriers: suitable models for all the IP blocks may not be available and when they are available then they may be in RTL only, lacking corresponding transaction-level models.

In this Tutorial we will address methodologies for performance analysis of advanced ARM interconnect, as well as approaches of hybrid execution for software bring-up, linking abstract simulation models with more detailed models of IP to create a hybrid simulation platform. The exploration of these topics will be illustrated through use of a case study where this approach has been utilized in practice.
Poonacha Kongetira is a seasoned leader with 20 years of engineering experience delivering products in high performance and mobile computing. Prior to NetSpeed Systems, Poonacha was a Senior Director at NVIDIA Corporation in Bangalore, India where he served as the site leader for NVIDIA's Bangalore Development Center managing a 700-person team. Prior to NVIDIA, Poonacha served as Director of Engineering at Sun Microsystems, Inc. and Afara Websystems. Poonacha holds a Master of Science degree in Electrical Engineering from Purdue University and a Bachelor of Engineering degree from Birla Institute of Technology and Science in India.

Nick Heaton is a Distinguished Engineer at Cadence Design Systems and currently is Architect and Group manager for the Interconnect Workbench, a comprehensive suite of tools for automating verification, performance analysis and debug of SoC Interconnects. The solution provides complete push-button capabilities for all ARM Interconnects including NIC-301, NIC-400 and CCI-400 products. Nick is an SoC development expert with 15+ years Silicon Design experience and 10+ years Advanced Verification experience managing highly skilled, cross-functional global teams after he graduated from Brunel University, Southall, United Kingdom.

Robert Kaye is a Technical Specialist at ARM focusing on system modeling. Robert has been with ARM for 8 years and prior to joining the Fast Models team last year was responsible for a broad portfolio of products in the System IP team including memory controllers. Robert has over 30 years of experience in the semiconductor industry. Before joining ARM he worked at Mentor Graphics on the development of hardware/software co-verification solutions and at Texas Instruments in EDA development and ASIC applications engineering.