Extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customer’s needs and market and technology trends. While adaptability of software components is straightforward, products include hardware accelerators –for reasons of performance and power efficiency- that also need to adapt to the new requirements. Hardware solutions can achieve high performance, and software solutions can easily adapt to the new set of threats, but neither can achieve flexibility and high performance at the same time.
Reconfigurable logic allows the definition of new functions to be defined in hardware units, combining hardware speed and efficiency, with ability to adapt and cope in a cost effective way with expanding functionality, changing environmental requirements, improvements in system features, changing protocols and data-coding standards, etc. However, designing, implementing and verifying reconfigurable hardware systems is harder compared to static ones.
This workshop aims at bringing together experts to discuss current technologies and trends in the reconfigurable computing area.
This workshop tends to focus on different topics/objectives of the design of computing systems:
1. To include reconfigurability as an explicit design concept: Current tools seem to lack a framework for system design where run-time adaptability, provided by dynamic hardware reconfiguration, becomes pivotal to computing system design. In this workshop we present cutting-edge research aiming at developing techniques and tools that analyze the structure and performance of the application, map it according to the capabilities of the underlying implementation platform, and provide a dynamically reconfigurable system implementation.
2. To effectively analyze and verify such reconfigurable systems: In order to guarantee that the final implementation corresponds to the application requirements and system specifications, we must have automated analysis, synthesis and verification algorithms. To validate the dynamic aspects of reconfiguration behavior, we will explore/present different design validation approaches such as simulation, hardware emulation and formal verification
3. To provide efficient and developer/user transparent runtime support for partial and dynamic reconfiguration: Assuming a partially reconfigurable system – either with a single or multiple FPGAs – we have to develop a runtime system that can efficiently handle the online scheduling and placement of reconfigurable system components, using dynamically adaptive schemes to optimize the system operation based on different functional and non-functional requirements defined by the user or the earlier tool-chain.
To support the above, the architecture has to expose some light-weight system monitors and control hooks to the runtime system. This will be one of the research challenges that will be investigated by our speakers during the workshop.
DAC has always been on the leading edge of new technologies working towards presenting breaking through research. In line with this observation this workshop will bring together researchers and industry for a wide ranging discussion on how reconfigurable computing has been around for a while and finally, nowadays, can be considered a mature technology to be effectively used.
DAC is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP).
DAC 2017 will be held in Austin, Texas, at the Austin Convention Center. Get details about travel, hotels, and area attractions in one convenient spot.