MONDAY June 02, 1:30pm - 3:00pm | Room 105
TOPIC AREA: IP
KEYWORD: GENERAL INTEREST
EVENT TYPE: IP TRACK
SESSION 4
Chair:
Warren Savage - IPextreme, Campbell, CA
IP companies regularly challenge the frontiers of design,
driven by insatiable customer demand for increasingly complex IP cores to use
in their products. In this session, we will see presentations that demonstrate
leading-edge solutions and reveal the stories behind how they were specified,
designed, verified, and validated.
| 4.1 | High Performance WIFI AFEs | |
| Speaker: | Priyank Shukla - Cadence Design Systems, Inc., Mumbai, India |
|
| Authors: | Priyank Shukla - Cadence Design Systems, Inc., Mumbai, India Venkatesh T.S. - Cadence Design Systems, Inc., San Jose, CA |
|
| 4.2 | MIPI® PHY Modules for SoC Development, Validation and Compliance Testing | |
| Speaker: | Surender Bhaskar - Arasan Chip Systems Inc., San Jose, CA |
|
| Authors: | Surender Bhaskar - Arasan Chip Systems Inc., San Jose, CA Sam W. Beal - Arasan Chip Systems Inc., San Jose, CA |
|
| 4.3 | Designing a Configurable NVM Express Subsystem | |
| Speaker: | Amit Saxena - Mobiveil, Inc., Milpitas, CA |
|
| Author: | Amit Saxena - Mobiveil, Inc., Milpitas, CA |
|
