THURSDAY June 05, 3:30pm - 5:00pm | Room 305
TOPIC AREA: EDA
KEYWORD: SYNTHESIS\FPGAS
EVENT TYPE: RESEARCH PAPER SESSION

SESSION 45
The Fast and the Fixable: Parallel CAD, Better ECOs and Smaller Chips
Chair:
Zhiru Zhang - Cornell Univ., Ithaca, NY
Speed is everything in car racing and chip development; how can we go faster without crashing? Will more pistons (processors) get us home faster? Can we clock a chip faster than the speed limit, and just pay the tickets? Can we drive flat out, and use our ECO toolbox to fix a blown engine?  Maybe timed traffic lights are the problem, and we should ignore them and drive asynchronously?  Cars are using more composite materials; should synthesis should use new components too, like Majority-Inverter Graphs? For the answer to these questions and more, take this session for a test drive.

45.1TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis
 Speaker: Mahmoud A. Elbayoumi - Virginia Polytechnic Institute and State Univ., Blacksburg, VA
 Authors: Mahmoud A. Elbayoumi - Virginia Polytechnic Institute and State Univ., Blacksburg, VA
Mihir Choudhury - IBM T.J. Watson Research Center, Yorktown Heights, NY
Victor Kravet - IBM T.J. Watson Research Center, Yorktown Heights, NY
Andrew Sullivan - IBM T.J. Watson Research Center, Yorktown Heights, NY
Michael Hsiao - Virginia Polytechnic Institute and State Univ., Blacksburg, VA
Mustafa Y. Einainay - Alexandria Univ., Alexandria, Egypt
45.2Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-Offs
 Speaker: Kan Shi - Imperial College London, United Kingdom
 Authors: Kan Shi - Imperial College London, United Kingdom
David Boland - Imperial College London, United Kingdom
Edward Stott - Imperial College London, United Kingdom
Samuel Bayliss - Imperial College London, United Kingdom
George A. Constantinides - Imperial College London, United Kingdom
45.3Functional ECO Using Metal-Configurable Gate-Array Spare Cells
 Speaker: Hua-Yu Chang - National Taiwan Univ., Taipei, Taiwan
 Authors: Hua-Yu Chang - National Taiwan Univ., Taipei, Taiwan
Iris Hui-Ru Jiang - National Chiao Tung Univ. , Hsinchu, Taiwan
Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan
45.4Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits
 Speaker: Chi-Chuan Chuang - National Taiwan Univ., Taipei, Taiwan
 Authors: Chi-Chuan Chuang - National Taiwan Univ., Taipei, Taiwan
Yi-Hsiang Lai - National Taiwan Univ., Taipei, Taiwan
Jie-Hong (Roland) Jiang - National Taiwan Univ., Taipei, Taiwan
45.5Parallel FPGA Routing based on the Operator Formulation
 Speaker: Yehdhih Ould Mohamed Moctar - Univ. of California, Riverside, CA
 Authors: Yehdhih Ould Mohamed Moctar - Univ. of California, Riverside, CA
Philip Brisk - Univ. of California, Riverside, CA
45.6Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization
 Speaker: Luca Amaru - École Polytechniquecole Polytechnique Fédérale de Lausanne, Switzerland
 Authors: Luca Amaru - École Polytechniquecole Polytechnique Fédérale de Lausanne, Switzerland
Pierre-Emmanuel Gaillardon - École Polytechniquecole Polytechnique Fédérale de Lausanne, Switzerland
Giovanni De Micheli - École Polytechniquecole Polytechnique Fédérale de Lausanne, Switzerland