It's widely acknowledged that verification is the bottle neck in today's design cycle. Verification approaches are always evolving to find new and innovate ways to solve more complex problems that are the norm in the Giga-Scale era. We've seen test bench methodologies change from manual directed test case approach to object orientated coverage driven, UVM methodology, we've seen formal techniques adopted and then refined to an "apps" based approach to allow for wider adoption, etc.
With the ever increasing complexity of today's chips and systems leading edge companies are looking for ways to speed the verification process and scale to large chips while meeting expanded complexity due to the drive to system verification. The invited speakers in this session will explore methodologies and flows to address the verification challenges of tomorrow.
|70.1||Aspect-Oriented Design - Optimizing SoC Verification Via Separation of Concerns|
|Speaker:||Wolfgang Roesner - IBM Server and Technology Group, Austin, TX
|Author:||Wolfgang Roesner - IBM Server and Technology Group, Austin, TX
|70.2||Virtual Platform/Emulation Hybrids: Combining Fast Software Execution and RTL Accuracy|
|Speaker:||Robert Kaye - ARM Ltd., Cambridge, United Kingdom
|Author:||Robert Kaye - ARM Ltd., Cambridge, United Kingdom
|70.3||Bridging the Gap Between Pre-Silicon Verification and Post Silicon Validation|
|Speaker:||Anshu Nadkarni - Nvidia Corp., Santa Clara, CA
|Authors:||Anshu Nadkarni - Nvidia Corp., Santa Clara, CA
Kiran Sama - Nvidia Corp., Austin, TX
Nathan Wooster - Nvidia Corp., Austin, TX
|70.4||Reducing Time to Market with Accelerated SW-HW Verification|
|Speaker:||Rajesh Goel - Qualcomm, Inc., San Diego, CA
|Authors:||Rajesh Goel - Qualcomm, Inc., San Diego, CA
Vishnu Renwa - Qualcomm, Inc., San Diego, CA
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