MONDAY June 08, 10:30am - 12:00pm | Room 302
TOPIC AREA: EDA
KEYWORD: GENERAL INTEREST
EVENT TYPE: MONDAY TUTORIAL
Tutorial 2: 2.5D/3D Memory & Logic Integration: Tools, Methodologies, Requirement and Infrastructure

Speakers:
Farhang Yazdani - BroadPak Corp., San Jose, CA
John Park - Mentor, A Siemens Business, Longmont, CO
Rajiv V. Joshi - IBM T.J. Watson Research Center, Yorktown Heights, NY
Organizer:
Farhang Yazdani - BroadPak Corp., San Jose, CA
Prospects of 2.5D/3D integration technology to break the memory and logic wall has prompted the memory makers to develop lower power and higher bandwidth devices. These devices are formed by stacking DRAMs in 3D configuration using Through Silicon Via (TSV). Due to large number of micro bumps, silicon interposer is typically used as carrier of choice to integrate these devices with multiple logic dies. Successful integration of these devices with logic dies on interposer, package and Board requires innovative low power logic design techniques, co-design methodology, advanced EDA tools, manufacturing requirement and supply chain infrastructure. Due to thermal requirement, low power logic design plays a critical role in producing a cost effective and reliable 2.5D/3D system.

This session provides the fundamental knowledge, individual skill sets and the most recent state of the art technologies used for 2.5D/3D integration. In particular we present low cost silicon interposer, low power logic design techniques and EDA tools and methodologies to perform system co-design.
Biography: FARHANG YAZDANI is the President and CEO of BroadPak Corporation, providing total solution and technologies to develop and launch secured 2.5D/3D products. Through his 17 years with the industry, he has served in various technical, management, and advisory positions with leading semiconductor companies worldwide. He is a frequent speaker at international events. He has numerous publications and IPs in the area of Packaging and Assembly, serves on various technical committees and is a frequent reviewer for IEEE Journal of Advanced Packaging. He received his undergraduate and graduate degrees in Chemical Engineering and Mechanical Engineering from the University of Washington, Seattle. He is a member of AICHE, ASME, IEEE, IMAPS, SPE and the Society of Rheology.
Biography: JOHN PARK brings 30 years of design tool experience to his role as Market Development Manager and Methodology Architect for the System Design Division at Mentor Graphics. Using his design experience in IC place & route, Package substrate design and PCB layout, he has developed robust cross-platform solutions that have helped define and drive the co-design market.

In his current role he serves as the Product Architect for Xpedition Package Integrator. Mr. Park studied microelectronics at California State University, Fullerton and holds a Certified Interconnect Designer certificate
Biography: Dr. RAJIV V. JOSHI is a research staff member at T. J. Watson research center, IBM. He received his B.Tech I.I.T (Bombay), M.S (M.I.T) and Dr. Eng. Sc. (Columbia University). has over 200 US patents and over 350 including international patents. He has authored and co-authored over 175 papers.