TUESDAY June 09, 10:30am - 12:00pm | Room 105
- Device drive strength selection is limited by Fin count granularity
- The vertical nature of FinFET transistors lead to a significant increase in cell input capacitance which forces logic cell usage to be reconsidered.
- Both Fin quantization and input capacitance can lead to an increase in dynamic power.
- Lag in metal design rule scaling due to more stringent DFM rule requirements.
- Ever increasing logic power densities in complex SOCs combined with increasing metal resistances increase the metal resource overhead to provide a robust power distribution for SOCs, which in turn puts additional pressure on signal routing congestion and achievable gate densities.
|17.1||FinFET Design Tools and Flows – Why Do You Need It! How Do You Get It?|
|Speaker:||Kuang-Kuo Lin - Samsung Electronics America, Inc., Milpitas, CA
|Author:||Kuang-Kuo Lin - Samsung Electronics America, Inc., Milpitas, CA
|17.2||FinFET Implementation Roller Coaster - What Is Not So Planar|
|Speaker:||Benjamin Mbouombouo - Avago Technologies, San Jose, CA
|Author:||Benjamin Mbouombouo - Avago Technologies, San Jose, CA
|17.3||Seeing Double? How Multiple Patterning Affects FinFET Designs at 16nm/14nm and Beyond|
|Speaker:||Brian Cline - Arm, Ltd., Austin, TX
|Author:||Brian Cline - Arm, Ltd., Austin, TX