From all appearances, emulation is about to take over domination of the verification space from the 30-year old work horse, simulation. The number of use models is expanding, as well as features and capabilities. Simulation experts, however, aren’t eager to wave the white flag and, in fact, point to the rapid adoption of formal verification that continues simulation’s value. Questions to be debated:
The format will be entertaining but informative with differing views and some conflict. Panelists will describe the various use models for emulation and explain how and why simulation has been so effective for so long. They will debate whether the simulation/formal verification flow works more effectively than a simulation/emulation flow. Finally, they will be asked to present their views on the evolution of verification in general and predictions about what’s coming next. John Sanguinetti, a noted simulation expert, will serve as moderator and have questions to stimulate the discussion, including how formal verification provides an orthogonal approach to simulation’s capabilities. Conversely, he will press panelists to explain why emulation doesn’t support formal verification as yet and, instead, focuses on execution performance. He will question the panel on the usability of each for hardware development and hardware/software integration, verification and the flexibility of both. Availability is another question that will be asked of the panel –– are both available to every engineer or used as a team tool? And, what are the training requirements? Cost considerations will be explored as the panel attempts to sort through the total cost of each, the cost per engineer and the cost per upgrade. Finally, John Sanguinetti will ask each panelist what is missing from the verification flow, such as emulation’s inability to offer support for analog and whether that will be possible in the future. Or, whether it will be a long-term hindrance.
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