THURSDAY June 22, 10:15am - 1:15pm | Ballroom F
TOPIC AREA: EDA
KEYWORD: TEST & VERIFICATION
EVENT TYPE: THURSDAY IS TRAINING DAY
Training Track 2, Part I: Formal Verification Using SystemVerilog Assertions
Speaker:
John Aynsley - Doulos , Ringwood, United Kingdom

This session will teach attendees how to use formal verification to verify RTL code by writing SystemVerilog Assertions (SVA). The emphasis will be on the practicalities of running today’s formal verification tools: how to write SVA, how to run the tools, how to get results from the tools, and what to do when formal proofs don’t finish. The session will cover all the main concepts and the pitfalls likely to be encountered when someone runs formal verification for the first time.

This session is aimed at RTL design and verification engineers who want to become familiar with the practical application of formal verification. Prior knowledge of SVA would be an advantage but is not required.

This track is taught by Doulos CTO John Aynsley, winner of the Accellera Systems Initiative 2012 Technical Excellence Award for his contribution to the development of language standards.


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