Much of the history of electronic design automation (EDA) has involved replacement of manual effort by automated processes. Place-and-route tools replaced hand layout, logic synthesis supplanted gate-level netlists, and constrained-random testbenches reduced or eliminated hand-written test vectors. Standardized formats used as input to the automation tools include SystemVerilog, Property Specification Language (PSL), and the Universal Verification Methodology (UVM).
In 2014, the Accellera standards organization observed that the level of automation provided by the UVM was insufficient to provide portability across all phases of chip verification. The Portable Stimulus Working Group (PSWG) was formed in December of that year to standardize “portable stimulus” models that can be used to generate tests at multiple integration levels and across multiple verification platforms. The PSWG is nearing completion of the first phase of its work to define a standard for portable test and stimulus models. The group has defined a declarative domain-specific language (DSL) with an alternative semantically-equivalent C++ input format to specify these models. Users can choose either format or mix and match models from different sources, as well as incorporate legacy code into the models via a direct procedural interface.
The new standard will raise the abstraction level of stimulus and test intent specification by modeling resource and data dependencies of behaviors, and composing them into scenarios using flow graphs. The abstract model can be analyzed by tools to solve constraints and dependencies at the scenario level, from which, along with a hardware/software interface library, target implementations may be automatically generated for the desired platforms.
This tutorial is an introduction to the standard, starting with background on the intended scope and defining goals. The main concepts behind the standard will be reviewed, including the key semantics underlying the model formats. Portable stimulus is not intended as a replacement for the UVM, but rather as a complement to it.The tutorial provides guidance on when and where the new methodology can be applied for maximum benefit on a chip project. Attendees will learn how to:
• Develop abstract, portable test and stimulus models for their chip designs
• Use constraints to guide randomization of both data and control flow
• Create low level driver sequences or reuse existing low-level sequences or drivers in the generation of tests • Generate tests tuned for IP, subsystem, and full system verification
• Execute the generated tests across all verification engines: virtual platforms, simulation, acceleration, emulation, FPGA prototype, and silicon in the bring-up lab
• Specify and gather coverage metrics at every step to assess verification completeness
The tutorial takes a building-block approach, starting with simple models and showing how these can be expanded and combined for more complex designs and more sophisticated verification scenarios. The ultimate goal is to generate use cases that reflect how the chip will be used in real applications.
Attendees will learn how to use the standard to specify and verify realistic system-level behavior, and will leave the tutorial educated on the value of portable stimulus and the basics of the standard.
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