TUESDAY June 20, 1:30pm - 3:00pm | Ballroom E
TOPIC AREA: EMBEDDED SYSTEMS, DESIGN
KEYWORD: SOC & EMBEDDED SYSTEM ARCHITECTURES, DIGITAL DESIGN, EMBEDDED SYSTEM SOFTWARE
EVENT TYPE: INVITED PRESENTATIONS
SESSION 23
Chair:
Rick O'Connor - RISC-V International, Ottawa, ON, Canada
Organizer:
Robert Oshana - NXP Semiconductors, Austin, TX
RISC-V (pronounced “risk-five”), an open instruction set architecture (ISA) that was originally designed at UC Berkeley to support computer architecture research and education, is an industry standard open ISA under the governance of the RISC-V Foundation. The RISC-V ISA is finding its way into applications ranging from IoT to high end servers and supercomputing. With the advent of RISC-V, which distills over 30 years of RISC processor research into an extensible instruction set that can be fully customized, hardware implementers are now able to build fully open-source based CPUs.
Thank You to Our Sponsor:
| 23.1 | RISC-V ISA and Foundation Overview | |
| Speaker: | Rick O'Connor - RISC-V International, Ottawa, ON, Canada |
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| Author: | Rick O'Connor - RISC-V International, Ottawa, ON, Canada |
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| 23.2 | RISC-V - A Free and Open ISA Enabling A Diversity of Core and Accelerator Choices | |
| Speaker: | Guy Lemieux - VectorBlox, Vancouver, BC, Canada |
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| Author: | Guy Lemieux - VectorBlox, Vancouver, BC, Canada |
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| 23.3 | RISC-V Tool Chain - An Example Implementation | |
| Speaker: | Tim Morin - Microsemi Corp., Dallas, TX |
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| Author: | Tim Morin - Microsemi Corp., Dallas, TX |
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| 23.4 | RISC-V OS Landscape | |
| Speaker: | Aditi Hilbert - Runtime, Redwood City, CA |
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| Author: | Aditi Hilbert - Runtime, Redwood City, CA |
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