WEDNESDAY June 21, 3:30pm - 5:00pm | Ballroom G
TOPIC AREA: IP, DESIGN
KEYWORD: SOC & EMBEDDED SYSTEM ARCHITECTURES, FPGA AND RECONFIGURABLE SYSTEMS, GENERAL INTEREST
EVENT TYPE: PANEL

SESSION 59
Have Third Party IPs Killed Internal IP Development?
Moderator:
Ann Steffora Mutschler - Semiconductor Engineering, San Jose, CA
Organizer:
Simon Rance - Arm, Ltd., Dallas, TX
 This panel will discuss the pros and cons of using third party IPs and their impact on the development of internal IPs. It will aim to address questions such as the following. If silicon proven third party IPs are available at a reasonable cost, does it make economic sense for semiconductor companies to create and manage their own IPs? Will the complex licensing schemes of third party IPs prove to be an increased liability for design companies? Will internal IP development be restricted to only non-standard custom IPs specific to their own internal needs?

Panelists:
Rich Wawrzyniak - Semico Research Corp., Green Bay, WI
Philippe Quinio - STMicroelectronics, Geneva, Switzerland
Ranjit Adhikary - ClioSoft, Inc., Fremont, CA
Daniel Cooley - Silicon Labs, Austin, TX
Andy Hawkins - Cypress Semiconductor Corp., San Jose, CA

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