THURSDAY June 28, 10:15am - 1:15pm | Room 3000
TOPIC AREA: EDA
KEYWORD: TEST & VERIFICATION
EVENT TYPE: THURSDAY IS TRAINING DAY
Track 1, Part I: How To Build Verification Environments in SystemVerilog
Speaker:
Eileen Hickey - Doulos , San Jose, CA

This session will teach the key SystemVerilog language skills needed to understand and build constrained random verification environments, as used by UVM. The emphasis will be on learning to apply the concepts of object-oriented programming to the creation of a re-usable test bench infrastructure. Language features will be taught using working code examples, which delegates can run immediately on the EDA Playground website and will be available to use and share after the class.

Topics to be taught include the object-oriented and constrained random language features of SystemVerilog, and more particularly how to use these language features to build a verification environment that includes a component hierarchy and transaction-level communication.

The knowledge taught in this session is an essential prerequisite to the afternoon session on UVM.


Sponsored by: