THURSDAY June 28, 2:15pm - 5:15pm | Room 3000
This session will teach the basics of UVM, the Universal Verification Methodology for SystemVerilog, by taking advantage of Doulos’ Easier™ UVM Coding Guidelines and Code Generator. All the main concepts of UVM will be taught using working code examples. By running the Easier™ UVM Code Generator on the EDA Playground website, delegates will be able to run UVM examples immediately, experiment with what they have learned, and share their examples with others after the class.
The session is aimed at hands-on engineers who want to start writing UVM code themselves and are looking for some specific advice on the best place to start, the right UVM features and coding idiom to use, and the pitfalls to avoid.