WEDNESDAY June 27, 1:30pm - 3:00pm | Room 2008
The Accellera Portable Test and Stimulus Standard is the next inflection point in IP verification and system-level validation productivity. Continuing the evolution of verification standards from SystemVerilog to UVM and now Portable Stimulus, verification engineers can now apply the proven techniques of constrained randomization and abstraction at the scenario level . The standard promotes the declarative specification of abstract behaviors to be associated with design and/or verification IP components in the system, allowing test writers to compose the IP-specific behaviors into an abstract specification of their verification intent for the system-under-test. Tools will then use automation to create multiple scenarios that model the critical intent while exploring the scenario space of the system-under-test. The resulting scenarios are implemented on different platforms throughout the verification flow, including virtual platforms, simulation, emulation, FPGA prototyping and post-silicon. The panel will explore the impact that the new Portable Test and Stimulus Standard will have on both design and verification IP, and the overall verification ecosystem.
With a variety of user perspectives, including Working Group participants as well as experienced and prospective user companies, the panel will address the following questions, as well as responding to audience questions as well:
• How will Portable Stimulus impact Verification IP? Design IP?
• Should Portable Stimulus become part of the default package delivered with an IP?
• Is Portable Stimulus an opportunity to bring design engineers more into the verification process? If so, how?
• Will RTL verification engineers and embedded software developers really use the same tool?
• Will Portable Stimulus complement or replace UVM?
• Is Portable Stimulus an evolution of verification or is it a revolution?
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