KEYWORD: LOW-POWER & RELIABILITY, ARCHITECTURE & SYSTEM DESIGN, ANALOG & MIXED-SIGNAL DESIGN
EVENT TYPE: IP TRACK PANEL
Minimizing IC Power Consumption with PPA Optimized IPs
John Blyler - JB Systems & Portland State Univ., Portland, OR
Farzad Zarrinfar - Mentor, A Siemens Business, Fremont, CA
Low power techniques are essential for introducing differentiated products to gain/keep market share. Applications like Artificial Intelligence, IOT, Deep Learning, Automotive, Virtual Reality, and wearable computing are transforming semiconductor industry and driving for low power IP strategies. In this panel, implementation techniques and tradeoffs for designing ultra Low-power SIP (Semiconductor IP), SOCs, ASSPs, and ASICs will be presented. These techniques are critical for battery-powered devices as well as reduction of packaging cost. IP suppliers and EDA vendors now offer low-power IPs as well as optimization tools. Topics such as FinFet and FDSOI devices will be compared with planar CMOS. Designers also apply advanced techniques by reduced voltage or Dynamic Voltage & Frequency Scaling (DVFS), power shutdown, dual-rail memory IPs, shutoff modes, and retention logic with resource sharing. Advanced low-power designs could have over 30 different power modes and power domains will be discussed.
Lluis Paris - Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA Aditya Mukherjee - Microsoft Corporation, Mountain View, CA Sarvesh Shrivastava - TDK Corp., San Jose, CA Tuomas Hollman - Minima Processor Oy, Fremont, CA Frederic Renoux - Dolphin Integration, Grenoble, France Saurabh Shrimal - Mentor, A Siemens Business, Noida, India