The panel will discuss emerging design implementation and signoff challenges for sub-7nm IP and SoC designs. Will ML/DL/AI innovations in EDA offer opportunities to meet the tough PPAR (Power, Performance, Area and reliability) goals and enable designers to shift left in TTR and TTM standards demanded by various verticals ranging from Autonomous, 5G, HPC, AI and next-generation of pervasive connectivity/mobility applications.
Dynamic voltage drop and its impact on timing
Role of emulation in analyzing thousands of real-life
Synthesis-Place & Route challenges to reduce the new
"Design Capability Design Gap" (Ref: Prof. A. Kahng)
Reliability challenges for > 15 years life time including
EM, thermal, ESD, EOS, aging, etc.
On-chip and off-chip EM Noise coupling
Comprehensive mission profile coverage due to many cores/IPs
Multi-stacking WoW 3DIC for AI/5G applications with multiple
Role of ML/DL/AI in EDA
Brucek Khailany - NVIDIA Corp., San Jose, CA Levent Burak Kara - Carnegie Mellon Univ., Pittsburgh, PA Mallik Tatipamula - Ericsson, Silicon Valley, CA Dr. Duane Boning - Massachusetts Institute of Technology, Boston, MA Sorin Dobre - Qualcomm Technologies, Inc., San Diego, CA