KEYWORD: LOW POWER, ANALOG & MIXED SIGNAL, IMPLEMENTATION
EVENT TYPE: MONDAY TUTORIAL
Tutorial 1: Modern Recipes for Brewing the Inevitable Methodology for Today’s ICs: Low Power Mixed-Signal Design Verification
Lakshmanan Balasubramanian - Texas Instruments India Pvt. Ltd., Bengaluru, India Venkatraman Ramakrishnan - Texas Instruments India Pvt. Ltd., Bengaluru, India Aswani Kumar Golla - Texas Instruments India Pvt. Ltd., Bengaluru, India Zhong Fon - Cadence Design Systems, Inc., San Jose, CA
Vijaykumar Sankaran - Cadence Design Systems, India Pvt. Ltd., Bengaluru, India Lakshmanan Balasubramanian - Texas Instruments India Pvt. Ltd., Bengaluru, India Venkatraman Ramakrishnan - Texas Instruments India Pvt. Ltd., Bengaluru, India
Ever-evolving markets like automotive, industrial, embedded consumer applications, and emerging markets like IoT, home automation, etc., are the key drivers of today’s complex power-managed electronic systems containing integrated digital, analog, RF, and power management content. Along with the complexity of such designs comes the inherent challenges in design verification at IP, subsystem, and SoC levels, keeping in mind various intricacies involved at different abstraction levels, viz., RTL and gate level (GL). The fundamental specification to perform design verification at any level of abstraction is that of the power supply, which in this context can be termed as the power intent (PI) specification. The hunger for low power and ultra-low power designs is increasing with growth in the number of devices integrated in today’s ICs. This mandates the need for advanced low-power design techniques utilizing industry-standard PI information such as Common Power Format (CPF), a power-domain centric PI format, and IEEE 1801, a power-supply network-centric PI format. Also, there is an obvious need for seamless support of such PI information across tools meant for design verification, PI validation, and design implementation to ensure quality signoff for both custom and semi-custom design styles.
Traditionally, design and verification of low-power ICs has been carried on with one of these PI specification formats. Design automation (DA) tools including simulators and synthesis tools would infer this PI specification to associate various blocks in the design with their respective power domains. Thus, PI data was entered only once and was used consistently by all the tools for identifying and inserting level shifters, isolation cells, retention flops, always-on cells, and power-gating switches wherever needed. Verification engineers would also carry out mixed-signal verification by replacing analog blocks in the design with real number (RN) behavioral models that constitute DMS simulations and with transistor-level (TL) models that constitute AMS simulations. Usually the PI information of such analog blocks would not contain any core low-power data, but just represent the PI information for the blocks with a module name, boundary ports, and the power modes. Those PI abstractions are termed as macro model. For mixed-signal simulations, PI macro model had to be inferred to pass on supply voltages from testbench or from internal on-chip supply such as LDO to the analog blocks in TL. This gave rise to the need and support of domain mapping, wherein the simulation tools would map the power domains of macro-model PI with the power domains in the testbench, thereby propagating the supply from source to TL analog blocks inside the DUT. As this technique worked only for analog blocks that have macro-model PI, over time simulation tools were enhanced so that the technique was extended even for blocks without macro-model PI but containing design PI. There are also analog-digital boundaries in a mixed-signal design that require interface elements (IE), and these IE would use the PI files of the corresponding digital blocks to infer the supply voltage for conversion.