KEYWORD: FRONT END DESIGN, BACK END DESIGN, IMPLEMENTATION
EVENT TYPE: MONDAY TUTORIAL
Tutorial 4: Machine Learning in Digital IC Design and EDA: Latest Results and Outlook
Mark Ren - NVIDIA Corp., Austin, TX Sreeram Chandrasekar - Cadence Design Systems, Inc., San Jose, CA
Jiang Hu - Texas A&M Univ., College Station, TX
In recent years, EDA tools and flows have faced ever-greater challenges in delivering complex chip designs within fast turnaround times. Meanwhile, vibrant progress of machine learning technologies has opened a new avenue for transformative improvement of EDA and IC design. This tutorial is to introduce EDA-relevant machine learning knowledge and applications in the scope centered around main design flows from RTL to GDSII. It will cover CNN based power prediction, Fully Convolutional Network (FCN) based DRC prediction, Graph Convolution Network based testability analysis and enhancement, and applications of reinforcement learning in combinatorial optimization and logic circuit optimization. Practical issues encountered with machine learning applications will be discussed, including data imbalance, feature selection, model selection and machine learning model hyper-parameter tuning. This tutorial will demonstrate applications of SVM, Random Forest, as well as CNN/FCN, to timing and signal integrity predictions, and how they help improve design optimization to achieve better Quality of Results. It will also show how ML can be integrated in the IC design flow, and a framework for leveraging data analytics and machine learning in the IC design flow will be discussed. Finally, this tutorial will provide an outlook for future research and development directions, and set out high value targets now and in the long term. It will cover what problems can be addressed in the near future, what are key challenges for researchers and practitioners, and what steps should be taken to better realize the potential value offered by machine learning in EDA and IC design.