TUESDAY June 04, 5:00pm - 6:00pm | Exhibit Floor
KEYWORD: ANY
EVENT TYPE: NETWORKING
Designer/IP Track Poster Networking Reception
During the poster presentation, you will interact directly with poster presenters in a small group setting.

As the limited time available in the Designer/IP Track session program was exceeded by the quantity of great submitted content, we present the following posters in the Designer/IP Track Poster Session held Tuesday, June 4 from 5:00 to 6:00pm on the Exhibit Floor.

Thank you to our Designer Track and IP Track Sponsors:


124.1Machine Learning Techniques for Minimizing PVT Corner Analyses and Library Validation
 Speaker: Prateek Pendyala - Intel Technology India Pvt. Ltd., Bangalore, India
 Authors: Prateek Pendyala - Intel Technology India Pvt. Ltd., Bangalore, India
Akash Hegde - Carnegie Mellon Univ., Pittsburgh, PA
Suryansh Sahota - Intel Technology India Pvt. Ltd., Bangalore, India
124.2Comprehensive Analog Layout Constraint Verification for Matching Devices
 Speaker: Saburo Hojo - Renesas Electronics Corp., Kodaira-shi, Japan
 Authors: Hirokazu Kitamura - Renesas Electronics Corp., Takasaki-shi, Japan
Saburo Hojo - Renesas Electronics Corp., Kodaira-shi, Japan
Kazuyuki Oya - Mentor, A Siemens Business, SHinagawa-ku, Japan
Toshiyuki Usui - Hitachi Ltd., Yokohama, Japan
124.3Managing Electrical Reliability During Layout Implementation
 Speakers: Vishesh Kumar - Cadence Design Systems, India Pvt. Ltd. & STMicroelectronics, Noida, India
Atul Bhargava - STMicroelectronics, Greater Noida, India
 Authors: Atul Bhargava - STMicroelectronics, Greater Noida, India
Akshita Mishra - STMicroelectronics, Greater Noida, India
Vishesh Kumar - Cadence Design Systems, India Pvt. Ltd. & STMicroelectronics, Noida, India
124.4System Level Power – Thermal Analysis using Computational Fluid Dynamics (CFD) Simulation and Machine Learning
 Speaker: Yunhyeok Im - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
 Authors: Wook Kim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Yunhyeok Im - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Youngsang Cho - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Joohee Choung - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Myunghoon Lee - ANSYS, Inc., Seoul-si, Republic of Korea
Varmsi Krishna Yaddanapudi - ANSYS, Inc., Balgalore, India
124.5Solving IP Quality Challenges in Complex IP
 Speaker: Kalyani Challa - Synopsys, Inc., Mountain View, CA
 Authors: Kalyani Challa - Synopsys, Inc., Mountain View, CA
Curtis M. Webster - Synopsys, Inc., Mountain View, CA
124.6Rapid Prototyping of Dynamic Voltage Drop using Combinations of Block Level Scenarios
 Speaker: Byunghyun Lee - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
 Authors: Byunghyun Lee - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Dongyoun Yi - Samsung Electronics Co., Ltd. & Seoul National Univ., Yongin, Republic of Korea
Yongho Lee - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Mathew J. Kaipanatu - ANSYS, Inc., Bengaluru, India
Rahul Rajan - ANSYS, Inc., San Jose, CA
Suresh K. Mantena - ANSYS, Inc., Bengaluru, India
Sankar Ramachandran - ANSYS, Inc. & Apache Design Solutions, Inc., Bangalore, India
124.7Enabling Exhaustive Reset Verification in Intel Design
 Speaker: Rohit K. Sinha - Intel Technology India Pvt. Ltd., Bangalore, India
 Author: Rohit K. Sinha - Intel Technology India Pvt. Ltd., Bangalore, India
124.8Hybrid Configurable Platform for HW&SW Co-development and Co-validation
 Speaker: Hyunjae Woo - Samsung Electronics Co., Ltd., Gyeonggi-do, Republic of Korea
 Authors: Hyunjae Woo - Samsung Electronics Co., Ltd., Gyeonggi-do, Republic of Korea
Youngsik Kim - Samsung Electronics Co., Ltd., Gyeonggi-do, Republic of Korea
Seonil B. Choi - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
124.9Pin FMEA of TPS65313 Device using Analog Fault Simulation
 Speaker: Tulong Yang - Texas Instruments, Inc., Dallas, TX
 Authors: Tulong Yang - Texas Instruments, Inc., Dallas, TX
Vijaykumar Sankaran - Cadence Design Systems, India Pvt. Ltd., Bengaluru, India
Chanakya K V - Texas Instruments India Pvt. Ltd., Bengaluru, India
Ayesha Chowdhury - Texas Instruments, Inc., Dallas, TX
Tahsin Alim - Texas Instruments, Inc., Dallas, TX
Samir Camdzic - Texas Instruments, Inc., Freising, Germany
Sumit Kumar - Texas Instruments India Pvt. Ltd., Bengaluru, India
Amit Bajaj - Cadence Design Systems, India Pvt. Ltd., Noida, India
Victor Zhuk - Cadence Design Systems, Inc., San Jose, CA
124.10A Low-power Triple-Vdd Dual-core Motion Estimation Chip Design and Implementation for a Wireless Panoramic Endoscopy
 Speaker: Ching-Hwa Cheng - Feng Chia Univ., Taichung, Taiwan
 Author: Ching-Hwa Cheng - Feng Chia Univ., Taichung, Taiwan
124.11Customizing FPGA Implementation Flows for Domain-specific Applications
 Speaker: Chris Lavin - Xilinx Inc., San Jose, CA
 Authors: Chris Lavin - Xilinx Inc., San Jose, CA
Alireza Kaviani - Xilinx Inc., San Jose, CA
124.12A Continuous Microprocessor Delivery Pipeline using Feature based Development
 Speaker: Gerrit Koch - IBM Deutschland Research & Development GmbH, Boeblingen, Germany
 Authors: Eduard Herkel - IBM Deutschland Research & Development GmbH, Boeblingen, Germany
Gerrit Koch - IBM Deutschland Research & Development GmbH, Boeblingen, Germany
Bodo Hoppe - IBM Deutschland Research & Development GmbH, Boeblingen, Germany
124.13Low Power Validation of Heterogeneous SoCs using Portable Stimulus Standard
 Speaker: Joydeep Maitra - Intel Technology India Pvt. Ltd., Bengaluru, India
 Authors: Joydeep Maitra - Intel Technology India Pvt. Ltd., Bengaluru, India
Vikash K. Singh - Intel Technology India Pvt. Ltd., Bengaluru, India
124.14A Transistor Level IR-drop based Method to Characterize an Accurate and Compact Model of an IP for SoC Level IR-EM Analysis
 Speaker: Paul Mathew - NXP Semiconductors, Noida, India
 Authors: Paul Mathew - NXP Semiconductors, Noida, India
Shivaraj Byru - NXP Semiconductors, Noida, India
Anant Narain - ANSYS, Inc., Noida, India
Akarshan Arora - NXP Semiconductors, Noida, India
124.15A Fast and Accurate Solution to Verify Layout Efficiency and Reliability for Power Management IC(PMIC) Design
 Speaker: Xuan Wang - HiSilicon, Shanghai, China
 Authors: Xuan Wang - HiSilicon, Shanghai, China
Jie Cheng - ANSYS, Inc., Shanghai, China
Biran Li - HiSilicon, Shanghai, China
Hong Jia - ANSYS, Inc., Shanghai, China
124.16A Smart RTL Linting Tool with Auto-correction
 Speaker: Khaled S. Mohamed - Mentor, A Siemens Business, Cairo, Egypt
 Author: Khaled S. Mohamed - Mentor, A Siemens Business, Cairo, Egypt
124.17Accurate and Correct-by-Construct Hold Margin Methodology for Standard Cells
 Speaker: Gaurav K. Varshney - Texas Instruments India Pvt. Ltd., Bangalore, India
 Authors: Gaurav K. Varshney - Texas Instruments India Pvt. Ltd., Bangalore, India
Rashmi Sachan - Texas Instruments India Pvt. Ltd., Bangalore, India
Tanvi Sharma - Texas Instruments India Pvt. Ltd., Bangalore, India
124.18Congestion Aware Buffer Planner for Complex Design Structure
 Speaker: Mukesh D. Bagul - GLOBALFOUNDRIES, Bangalore, India
 Authors: Mukesh D. Bagul - GLOBALFOUNDRIES, Bangalore, India
Vishal Rajvedi - GLOBALFOUNDRIES & Avera Semiconductor LLC, Bangalore, India
124.19Enhancing Functional Debug Capabilities using ALLSCAN Test Structures
 Speaker: Hardik Bhagat - GLOBALFOUNDRIES, Bengaluru, India
 Authors: Hardik Bhagat - GLOBALFOUNDRIES, Bengaluru, India
Sreekanth Pai - GLOBALFOUNDRIES, Bangalore, India
Kavitha Shankar - GLOBALFOUNDRIES, Bangalore, India
Balaji Upputuri - GLOBALFOUNDRIES, Bangalore, India
124.20Improve Hardware Assurance (HwA) using FPGA IP in your ASICs and SoCs
 Speaker: Raymond Nijssen - Achronix Semiconductor Corp., Santa Clara, CA
 Authors: Raymond Nijssen - Achronix Semiconductor Corp., Santa Clara, CA
Quinn Jacobson - Achronix Semiconductor Corp., Santa Clara, CA
124.21STA Compatible Netlist CDC Methodology
 Speaker: Ankush Bagotra - Synopsys, Inc., Sunnyvale, CA
 Authors: Pratik Suthar - NVIDIA Corp., Bangalore, India
Ulhas Kotha - NVIDIA Corp., Bangalore, India
Ankush Bagotra - Synopsys, Inc., Sunnyvale, CA
Ravindra Nibandhe - Synopsys India Pvt. Ltd., Karnataka, India
124.22Application of Tempus Scope for Accelerated Timing Signoff
 Speaker: Tim Helvey - GLOBALFOUNDRIES & Avera Semiconductor, LLC, Rochester, MN
 Authors: Tim Helvey - GLOBALFOUNDRIES & Avera Semiconductor, LLC, Rochester, MN
Parth Lakhiya - Cyient & GLOBALFOUNDRIES, Pune, India
Jay Gaudani - GLOBALFOUNDRIES, Santa Clara, CA
Tim Sterczyk - Cyient & Avera Semiconductor LLC, Ottawa, Ontario, Canada
124.23A Novel Methodology for Fast PDN Sign-off by Slicing Long-vectors
 Speaker: Udayakumar Yedakuppam - Infineon Technologies, Bengaluru, India
 Authors: Udayakumar Yedakuppam - Infineon Technologies, Bengaluru, India
Soenke Grimpen - Infineon Technologies, Munich, Germany
Dileesh Jostin - ANSYS, Inc., Bangalore, India
Manali Khare - ANSYS, Inc., Bengaluru, India
124.24Early-stage Power Check Methodology for IP Power Audit
 Speaker: Jinsuk Youn - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
 Authors: Jinsuk Youn - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Jeongwon Kang - ANSYS, Inc., Seoul, Republic of Korea
Seonghoon Kim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Chul Rim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Naya Ha - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Kyungtae Do - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Jung Yun Choi - Samsung Electronics Co., Ltd., Yong-in, Republic of Korea
124.25Configurable Multi-protocol AUTOSAR-based Secure Communication Accelerator
 Speaker: Ahmed Hamed - Mentor, A Siemens Business, Cairo, Egypt
 Authors: Ahmed Hamed - Mentor, A Siemens Business, Cairo, Egypt
Mona Safar - Ain Shams Univ., Cairo, Egypt
M. Watheq El-Kharashi - Ain Shams Univ., Cairo, Egypt
Ashraf Salem - Mentor, A Siemens Business, Cairo, Egypt
124.26A Method to Build Clock Tree Comprehending Switching Activity to Address DVD in an SOC
 Speaker: Atul Garg - Texas Instruments India Pvt. Ltd., Bangalore, India
 Authors: Atul Garg - Texas Instruments India Pvt. Ltd., Bangalore, India
Venkatraman Ramakrishnan - Texas Instruments India Pvt. Ltd., Bangalore, India