MONDAY June 03, 1:30pm - 3:00pm | N260
TOPIC AREA: DESIGN, EDA
KEYWORD: BACK END DESIGN, LOW POWER, IMPLEMENTATION
EVENT TYPE: DESIGNER TRACK

SESSION 4
Power Bytes Delivered
Chair:
Badhri Uppiliappan - Analog Devices, Inc., Norwood, MA
This session will begin with a journey into improving power analysis for large and complex multi-voltage, multi-chip; followed by deeper exploration of various aspects of building and analyzing power grid networks and electro-migration from signoff perspectives.

Thank you to our Designer Track Sponsor:


4.1Efficient Multi Power Domain Analysis using IPD Flow
 Speaker: Jongyoon Jung - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
 Authors: Jongyoon Jung - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Aniket Deshmukh - Cadence Design Systems, Inc., Seongnam-Si, Republic of Korea
Pawan D. Gandhi - Cadence Design Systems, Inc. & BITS Pilani, Noida, India
Naresh Kumar - Cadence Design Systems, Inc., Uttar Pradesh, India
Arvind Veeravalli - Cadence Design Systems, Inc., Bengaluru, India
Ritika Govila - Cadence Design Systems, Inc., Bangalore, India
Jeannette Sutherland - Cadence Design Systems, Inc., Austin, TX
4.23D Stacked (Foveros) SOC Power Delivery Analysis Methodology for Predictable Silicon Success
 Speaker: Biswajit Patra - Intel Technology India Pvt. Ltd., Bangalore, India
 Authors: Biswajit Patra - Intel Technology India Pvt. Ltd., Bangalore, India
Ayan Roy Chowdhury - Intel Technology India Pvt. Ltd., Bangalore, India
4.3Two Different Approaches of Power Integrity Analysis and Correlate with On-chip measurement
 Speaker: Oscar Ou - MediaTek, Inc., San Jose, CA
 Authors: Chee Kong Ung - MediaTek, Inc., hsinchu city, Taiwan
Mizar Chang - MediaTek, Inc., hsinchu city, Taiwan
Sean Hwang - MediaTek, Inc., hsinchu city, Taiwan
Bihqui Tiang - MediaTek, Inc., hsinchu city, Taiwan
PeiShen Wei - ANSYS, Inc., Taipei, Taiwan
Ying-jiunn Lai - ANSYS, Inc., Taipei, Taiwan
ChanChiuan Lee - ANSYS, Inc., Taipei, Taiwan
Oscar Ou - MediaTek, Inc., San Jose, CA
4.4Electro-migration Reliability Verification of Gate Level Blocks for High Performance Microprocessors in Presence of Self-Heating
 Speaker: Nagu Dhanwada - IBM Corp., Poughkeepsie, NY
 Authors: Nagu Dhanwada - IBM Corp., Poughkeepsie, NY
Leon Sigal - IBM Research, Yorktown Heights, NY
David Kadzov - IBM Systems Group, Williston, VT
4.5A Multi-perspective Approach to IC Power Grid Development for 7nm Based Designs
 Speaker: Mahendrasing J. Patil - Intel Technology India Pvt. Ltd., Bangalore, India
 Authors: Mahendrasing J. Patil - Intel Technology India Pvt. Ltd., Bangalore, India
Ravi Teja Susarla - Intel Technology India Pvt. Ltd., Bangalore, India
Surendra Boosam Kota - Intel Technology India Pvt. Ltd., Bangalore, India
4.6Electromigration Signoff based on IR-drop Degradation Assessment
 Speaker: Valeriy Sukharev - Mentor, A Siemens Business, Fremont, CA
 Authors: Valeriy Sukharev - Mentor, A Siemens Business, Fremont, CA
Armen Kteyan - Mentor, A Siemens Business, Yerevan, Armenia
Jun-Ho Choy - Mentor, A Siemens Business, Fremont, CA
Farid N. Najm - Univ. of Toronto, Canada