WEDNESDAY June 05, 3:30pm - 5:00pm | N260
TOPIC AREA: MACHINE LEARNING/AI, EDA
KEYWORD: VERIFICATION/VALIDATION, FRONT END DESIGN, EMERGING TECHNOLOGIES
EVENT TYPE: DESIGNER TRACK

SESSION 66
Machine Learning and Front End Design
Chair:
Vikas Sachdeva - Real Intent, Inc., Sunnyvale, CA
For those of us in the hardware design world, Machine Learning impacts us in two major ways: as a tool to help us design and validate, and as a new style of design we must support. In this session we will discuss new and innovative approaches in both these areas.

Thank you to our Designer Track Sponsor:


66.1Improving Design Performance using Machine Learning in Synthesis
 Speaker: Gaurav K. Varshney - Texas Instruments India Pvt. Ltd., Bangalore, India
 Authors: Gaurav K. Varshney - Texas Instruments India Pvt. Ltd., Bangalore, India
Akshi Tomar - Texas Instruments India Pvt. Ltd., Bangalore, India
66.2High Confidence Early RTL Power Estimation with Machine Learning
 Speaker: Srinivas R. Jammula - Intel Corp., Bengaluru, India
 Authors: Ajay S. Bist - Intel Corp., Bangalore, India
Mahesh G. Vutukuri - Intel Technology India Pvt. Ltd. & Intel Corp., Bangalore, India
Srinivas R. Jammula - Intel Corp., Bengaluru, India
66.3Dedicated On-chip Network Hierarchies for Algorithm Acceleration
 Speaker: Kent Orthner - Achronix Semiconductor Corp., Santa Clara, United States
 Authors: Kent Orthner - Achronix Semiconductor Corp., Santa Clara, United States
Travis Johnson - Achronix Semiconductor Corp., Santa Clara, CA
66.4Virtual Methodology For Performance and Power Analysis of AI/ML SoC Using Emulation
 Speaker: Vikas Singhal - Mentor, A Siemens Business, Fremont, CA
 Authors: Vikas Singhal - Mentor, A Siemens Business, Fremont, CA
Debdutta Bhattacharya - Mentor, A Siemens Business, Fremont, CA
Ayub Khan - Mentor, A Siemens Business, Fremont, CA
66.5Arithmetic Datapath Design Exploration with Machine Learning
 Speaker: Mahesh G. Vutukuri - Intel Technology India Pvt. Ltd. & Intel Corp., Bangalore, India
 Authors: Mahesh G. Vutukuri - Intel Technology India Pvt. Ltd. & Intel Corp., Bangalore, India
Sreekanth Madgula - Intel Corp., Folsom, CA
Ashutosh Garg - Intel Corp., Folsom, CA
66.6Maximize TOPS (Tera Operations Per Second) per Watt for AI Chip using Early Power Analysis and Reduction
 Speaker: Ling Sun - Iluvatar CoreX Inc., Shanghai, China
 Authors: Ling Sun - Iluvatar CoreX Inc., Shanghai, China
Cheng Peng - ANSYS, Inc., Shanghai, China
Zhenhua Gan - Iluvatar CoreX Inc., Shanghai, China
Du Zhang - Iluvatar CoreX Inc., Shanghai, China