MONDAY June 03, 3:30pm - 5:00pm | N262
TOPIC AREA: DESIGN, EDA
KEYWORD: BACK END DESIGN, IMPLEMENTATION
EVENT TYPE: DESIGNER TRACK

SESSION 8
Time Space Continuum
Chair:
Natarajan Viswanathan - Cadence Design Systems, Inc.
Improving timing closure by applying new perspectives to change the search space of solutions are some key messages that get explored in this session.

Thank you to our Designer Track Sponsor:


8.1Coverage Improvement of Assertion Based SDC Verification at Early Design Phase
 Speaker: Nozomi Yunokuchi - Renesas Electronics Corp., Kodaira-shi, Japan
 Authors: Nozomi Yunokuchi - Renesas Electronics Corp., Kodaira-shi, Japan
Himanshu Bhatnagar - Excellicon Inc., Laguna Hills, CA
8.2Design Optimization and Implementation Methodology using Cells with Different Diffusion Breaks
 Speaker: Jae Hoon Kim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
 Authors: Jae Hoon Kim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Yongdeok Kim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Wootae Kim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Hyung-Ock Kim - Samsung Electronics Co., Ltd., Yongin, Republic of Korea
joonyoung Shin - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Jaewon Lee - Samsung Semiconductor, Inc., Hwasung-si, Republic of Korea
Jung Yun Choi - Samsung Electronics Co., Ltd., Yong-in, Republic of Korea
8.3An Advanced Method of Routing Optimization with 3D Coupling Aware To Improve Timing
 Speaker: Jialian Tang - Avera Semiconductor LLC & GLOBALFOUNDRIES, Shanghai, China
 Authors: Jialian Tang - Avera Semiconductor LLC & GLOBALFOUNDRIES, Shanghai, China
Baoguang Yan - Avera Semiconductor LLC & GLOBALFOUNDRIES, Beijing, China
Fengfeng Wu - Avera Semiconductor LLC & GLOBALFOUNDRIES, Beijing, China
Mike Trick - Avera Semiconductor LLC & GLOBALFOUNDRIES, Burlington, VT
8.4Local Layout Effect Aware Design Methodology for Performance Boost below 10nm FinFET Technology
 Speaker: Jae Hoon Kim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
 Authors: Jae Hoon Kim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Wootae Kim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Naya Ha - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Hyung-Ock Kim - Samsung Electronics Co., Ltd., Yongin, Republic of Korea
Sunik Heo - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Hyunjeong Roh - Samsung Electronics Co., Ltd and Seoul National Univ., Hwaseong, Republic of Korea
Hayoung Kim - Siemens Corp. & Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Yonghwan Kim - Samsung Electronics Co., Ltd., Seoul, Republic of Korea
Hyunwoo Kim - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Jung Yun Choi - Samsung Electronics Co., Ltd., Yong-in, Republic of Korea
8.5A Graph Based Modelling Of Multi Input Switching (MIS) in STA with Silicon Path Frequency Correlation
 Speaker: Amartya Mazumdar - NVIDIA Corp., Bangalore, India
 Authors: Amartya Mazumdar - NVIDIA Corp., Bangalore, India
Ulhas Kotha - NVIDIA Corp., Bangalore, India
Anshuman Seth - NVIDIA Corp., Bangalore, India
Tezaswi Raja - NVIDIA Corp., San Jose, CA
Reecha Jajodia - NVIDIA Corp., Bangalore, India
Jaison Kurien - NVIDIA Corp., Bangalore, India
Sarvesh Sharma - NVIDIA Corp., Bangalore, India
8.6Tile-based Automated Pipeline Floorplanning
 Speaker: Greg Ford - Avera Semiconductor LLC & GLOBALFOUNDRIES, Santa Clara, CA
 Author: Greg Ford - Avera Semiconductor LLC & GLOBALFOUNDRIES, Santa Clara, CA